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最新推荐文章于 2024-02-05 13:24:02 发布

justdemo

最新推荐文章于 2024-02-05 13:24:02 发布

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文章标签： Verilog HDL 图像处理像素运算硬件加速二维数组

本文链接：https://blog.csdn.net/justdemo/article/details/125958780

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这道题好像没有什么巧妙的办法，只有用for循环
解题如下：

module top_module(
    input clk,
    input load,
    input [255:0] data,
    output [255:0] q ); 
    
    integer i,j;
    integer m,n;
    integer x,y;

    // 18 * 18
    reg [304:-19] bq;

    // 16 * 16 -> 18 * 18
    always@(*) begin
        for(i = -1; i < 17; i += 1) begin
            for(j = -1; j < 17; j += 1) begin
                if(i == -1)m = 15;
                else if(i == 16)m = 0;
                else m = i;

                if(j == -1)n = 15;
                else if(j == 16)n = 0;
                else n = j;
                
                bq[i*18 + j] = q[m*16 + n];
            end
        end
    end
    
    reg [2:0] sum;
    always@(posedge clk) begin
        if(load)q <= data;
        else begin
            for(x = 0; x < 16; x += 1) begin
                for(y = 0; y < 16; y += 1) begin
                    sum = bq[x*18 + y + 1] + bq[x*18 + y - 1]
                    + bq[(x+1)*18 + y] + bq[(x+1)*18 + y + 1] + bq[(x+1)*18 + y - 1]
                    + bq[(x-1)*18 + y] + bq[(x-1)*18 + y + 1] + bq[(x-1)*18 + y - 1];
                    case(sum)
                        3'b010: q[x*16 + y] <= q[x*16 + y];
                        3'b011: q[x*16 + y] <= 1'b1;
                        default: q[x*16 + y] <= 1'b0;
                    endcase                    
                end
            end
        end
    end    

endmodule