HDLBits——Conwaylife

module top_module(
    input clk,
    input load,
    input [255:0] data,
    output [255:0] q ); 
      logic  [255:0] q1;
    logic [15:0][15:0]tmpp;
    assign tmpp = q1[255:0];
    assign q   = q1;
  
    function logic[255:0] check (input logic [15:0][15:0]tmp,input logic[255:0] q);
        integer x;
        integer y;
         bit [3:0] s;
        logic[255:0] out;
        integer left1;
        integer left2;
        integer right1;
        integer right2;
        
        logic[7:0] count;
        begin
            for(count = 0,x = 0; x<16; x=  x+1)
                for(y = 0;y<16;y= y+1,count = count + 1)
                    begin
                 s = 0;
                    if(x-1<0)
                       left1 = 4'd15;
                    else
                     left1 = x - 1;
                if(y-1<0)
                   left2 = 'd15;
                    else
                   left2 = y - 1;
                        if(x+1>15)
                       right1 = 4'd0;
                    else
                     right1 = x + 1;
                        if(y+1>15)
                     right2 = 4'd0;
                    else
                   right2 = y + 1;
                    
                    case(s+tmp[right1][y]+tmp[x][right2]+tmp[right1][right2]+tmp[left1][left2]+tmp[x][left2]+tmp[left1][right2]+tmp[right1][left2]+tmp[left1][y])
                        3:begin  out[count] = 1;end
                        2:begin  out[count]= q[count];end
                        default:begin  out[count] = 0; end
                    endcase 
            end
        end
        return out;
    endfunction
    always_comb
        begin
        end
    always_ff@(posedge clk)
        if(load)
            q1 <= data;
        else
            begin
            q1 <= check(tmpp,q1);
            end
endmodule