https://docs.espressif.com/projects/esp-idf/en/latest/esp32/security/flash-encryption.html#development-mode
使能
espefuse.py -p /dev/ttyUSB0 summary
Connecting....
Detecting chip type... ESP32
espefuse.py v3.0
EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value)
----------------------------------------------------------------------------------------
Calibration fuses:
BLK3_PART_RESERVE (BLOCK0): BLOCK3 partially served for ADC calibration data = False R/W (0b0)
ADC_VREF (BLOCK0): Voltage reference calibration = 1065 R/W (0b10101)
Config fuses:
XPD_SDIO_FORCE (BLOCK0): Ignore MTDI pin (GPIO12) for VDD_SDIO on reset = False R/W (0b0)
XPD_SDIO_REG (BLOCK0): If XPD_SDIO_FORCE, enable VDD_SDIO reg on reset = False R/W (0b0)
XPD_SDIO_TIEH (BLOCK0): If XPD_SDIO_FORCE & XPD_SDIO_REG = 1.8V R/W (0b0)
CLK8M_FREQ (BLOCK0): 8MHz clock freq override = 52 R/W (0x34)
SPI_PAD_CONFIG_CLK (BLOCK0): Override SD_CLK pad (GPIO6/SPICLK) = 0 R/W (0b00000)
SPI_PAD_CONFIG_Q (BLOCK0): Override SD_DATA_0 pad (GPIO7/SPIQ) = 0 R/W (0b00000)
SPI_PAD_CONFIG_D (BLOCK0): Override SD_DATA_1 pad (GPIO8/SPID) = 0 R/W (0b00000)
SPI_PAD_CONFIG_HD (BLOCK0): Override SD_DATA_2 pad (GPIO9/SPIHD) = 0 R/W (0b00000)
SPI_PAD_CONFIG_CS0 (BLOCK0): Override SD_CMD pad (GPIO11/SPICS0) = 0 R/W (0b00000)
DISABLE_SDIO_HOST (BLOCK0): Disable SDIO host = False R/W (0b0)
Efuse fuses:
WR_DIS (BLOCK0): Efuse write disable mask = 0 R/W (0x0000)
RD_DIS (BLOCK0): Efuse read disable mask = 0 R/W (0x0)
CODING_SCHEME (BLOCK0): Efuse variable block length scheme
= NONE (BLK1-3 len=256 bits) R/W (0b00)
KEY_STATUS (BLOCK0): Usage of efuse block 3 (reserved) = False R/W (0b0)
Identity fuses:
MAC (BLOCK0): Factory MAC Address
= c4:4f:33:7c:72:99 (CRC 0xfb OK) R/W
MAC_CRC (BLOCK0): CRC8 for factory MAC address = 251 R/W (0xfb)
CHIP_VER_REV1 (BLOCK0): Silicon Revision 1 = True R/W (0b1)
CHIP_VER_REV2 (BLOCK0): Silicon Revision 2 = False R/W (0b0)
CHIP_VERSION (BLOCK0): Reserved for future chip versions = 2 R/W (0b10)
CHIP_PACKAGE (BLOCK0): Chip package identifier = 0 R/W (0b000)
MAC_VERSION (BLOCK3): Version of the MAC field = 0 R/W (0x00)
Security fuses:
FLASH_CRYPT_CNT (BLOCK0): Flash encryption mode counter = 0 R/W (0b0000000)
UART_DOWNLOAD_DIS (BLOCK0): Disable UART download mode (ESP32 rev3 only) = False R/W (0b0)
FLASH_CRYPT_CONFIG (BLOCK0): Flash encryption config (key tweak bits) = 0 R/W (0x0)
CONSOLE_DEBUG_DISABLE (BLOCK0): Disable ROM BASIC interpreter fallback = True R/W (0b1)
ABS_DONE_0 (BLOCK0): Secure boot V1 is enabled for bootloader image = False R/W (0b0)
ABS_DONE_1 (BLOCK0): Secure boot V2 is enabled for bootloader image = False R/W (0b0)
JTAG_DISABLE (BLOCK0): Disable JTAG = False R/W (0b0)
DISABLE_DL_ENCRYPT (BLOCK0): Disable flash encryption in UART bootloader = False R/W (0b0)
DISABLE_DL_DECRYPT (BLOCK0): Disable flash decryption in UART bootloader = False R/W (0b0)
DISABLE_DL_CACHE (BLOCK0): Disable flash cache in UART bootloader = False R/W (0b0)
BLOCK1 (BLOCK1): Flash encryption key
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
BLOCK2 (BLOCK2): Secure boot key
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
BLOCK3 (BLOCK3): Variable Block 3
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
Flash voltage (VDD_SDIO) determined by GPIO12 on reset (High for 1.8V, Low/NC for 3.3V).
esptool.py --chip esp32 -p /dev/ttyUSB0 -b 460800 --before=default_reset --after=no_reset write_flash --flash_mode dio --flash_freq 40m --flash_size 2MB 0xf000 partition_table/partition-table.bin 0x1000 bootloader/bootloader.bin 0x20000 hello-world.bin
--- idf_monitor on /dev/ttyUSB0 115200 ---
--- Quit: Ctrl+] | Menu: Ctrl+T | Help: Ctrl+T followed by Ctrl+H ---
ets Jun 8 2016 00:22:57
rst:0x1 (POWERON_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0xee
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:2
load:0x3fff0030,len:4
load:0x3fff0034,len:8988
load:0x40078000,len:15276
ho 0 tail 12 room 4
load:0x40080400,len:4568
0x40080400: _init at ??:?
entry 0x400806f4
I (31) boot: ESP-IDF v4.2-dirty 2nd stage bootloader
I (31) boot: compile time 19:49:22
I (31) boot: chip revision: 1
I (34) boot_comm: chip revision: 1, min. bootloader chip revision: 0
I (41) boot.esp32: SPI Speed : 40MHz
I (46) boot.esp32: SPI Mode : DIO
I (50) boot.esp32: SPI Flash Size : 2MB
I (55) boot: Enabling RNG early entropy source...
I (60) boot: Partition Table:
I (64) boot: ## Label Usage Type ST Offset Length
I (71) boot: 0 nvs WiFi data 01 02 00010000 00006000
I (79) boot: 1 phy_init RF data 01 01 00016000 00001000
I (86) boot: 2 factory factory app 00 00 00020000 00100000
I (94) boot: End of partition table
I (98) boot_comm: chip revision: 1, min. application chip revision: 0
I (105) esp_image: segment 0: paddr=0x00020020 vaddr=0x3f400020 size=0x05d28 ( 23848) map
I (123) esp_image: segment 1: paddr=0x00025d50 vaddr=0x3ffb0000 size=0x020b0 ( 8368) load
I (127) esp_image: segment 2: paddr=0x00027e08 vaddr=0x40080000 size=0x00404 ( 1028) load
0x40080000: _WindowOverflow4 at /home/mali/esp/esp32/esp-idf-master/components/freertos/xtensa/xtensa_vectors.S:1730
I (132) esp_image: segment 3: paddr=0x00028214 vaddr=0x40080404 size=0x07e04 ( 32260) load
I (155) esp_image: segment 4: paddr=0x00030020 vaddr=0x400d0020 size=0x130d8 ( 78040) map
0x400d0020: _stext at ??:?
I (185) esp_image: segment 5: paddr=0x00043100 vaddr=0x40088208 size=0x01cc4 ( 7364) load
0x40088208: rtc_clk_cpu_freq_to_xtal at /home/mali/esp/esp32/esp-idf-master/components/soc/src/esp32/rtc_clk.c:431
I (194) boot: Loaded app from partition at offset 0x20000
I (194) boot: Checking flash encryption...
I (194) flash_encrypt: Generating new flash encryption key...
I (202) flash_encrypt: Read & write protecting new key...
I (208) flash_encrypt: Setting CRYPT_CONFIG efuse to 0xF
W (214) flash_encrypt: Not disabling UART bootloader encryption
I (221) flash_encrypt: Disable UART bootloader decryption...
I (227) flash_encrypt: Disable UART bootloader MMU cache...
I (233) flash_encrypt: Disable JTAG...
I (238) flash_encrypt: Disable ROM BASIC interpreter fallback...
I (256) boot_comm: chip revision: 1, min. application chip revision: 0
I (256) esp_image: segment 0: paddr=0x00001020 vaddr=0x3fff0030 size=0x00004 ( 4)
I (262) esp_image: segment 1: paddr=0x0000102c vaddr=0x3fff0034 size=0x0231c ( 8988)
I (274) esp_image: segment 2: paddr=0x00003350 vaddr=0x40078000 size=0x03bac ( 15276)
I (285) esp_image: segment 3: paddr=0x00006f04 vaddr=0x40080400 size=0x011d8 ( 4568)
0x40080400: _init at ??:?
I (764) boot_comm: chip revision: 1, min. application chip revision: 0
I (764) esp_image: segment 0: paddr=0x00020020 vaddr=0x3f400020 size=0x05d28 ( 23848) map
I (778) esp_image: segment 1: paddr=0x00025d50 vaddr=0x3ffb0000 size=0x020b0 ( 8368)
I (781) esp_image: segment 2: paddr=0x00027e08 vaddr=0x40080000 size=0x00404 ( 1028)
0x40080000: _WindowOverflow4 at /home/mali/esp/esp32/esp-idf-master/components/freertos/xtensa/xtensa_vectors.S:1730
I (786) esp_image: segment 3: paddr=0x00028214 vaddr=0x40080404 size=0x07e04 ( 32260)
I (807) esp_image: segment 4: paddr=0x00030020 vaddr=0x400d0020 size=0x130d8 ( 78040) map
0x400d0020: _stext at ??:?
I (837) esp_image: segment 5: paddr=0x00043100 vaddr=0x40088208 size=0x01cc4 ( 7364)
0x40088208: rtc_clk_cpu_freq_to_xtal at /home/mali/esp/esp32/esp-idf-master/components/soc/src/esp32/rtc_clk.c:431
I (840) flash_encrypt: Encrypting partition 2 at offset 0x20000...
I (14186) flash_encrypt: Flash encryption completed
I (14186) boot: Resetting with flash encryption enabled...
ets Jun 8 2016 00:22:57
rst:0x3 (SW_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0xee
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:2
load:0x3fff0030,len:4
load:0x3fff0034,len:8988
load:0x40078000,len:15276
ho 0 tail 12 room 4
load:0x40080400,len:4568
0x40080400: _init at ??:?
entry 0x400806f4
I (60) boot: ESP-IDF v4.2-dirty 2nd stage bootloader
I (60) boot: compile time 19:49:22
I (60) boot: chip revision: 1
I (64) boot_comm: chip revision: 1, min. bootloader chip revision: 0
I (71) boot.esp32: SPI Speed : 40MHz
I (76) boot.esp32: SPI Mode : DIO
I (80) boot.esp32: SPI Flash Size : 2MB
I (85) boot: Enabling RNG early entropy source...
I (90) boot: Partition Table:
I (94) boot: ## Label Usage Type ST Offset Length
I (101) boot: 0 nvs WiFi data 01 02 00010000 00006000
I (109) boot: 1 phy_init RF data 01 01 00016000 00001000
I (116) boot: 2 factory factory app 00 00 00020000 00100000
I (124) boot: End of partition table
I (128) boot_comm: chip revision: 1, min. application chip revision: 0
I (135) esp_image: segment 0: paddr=0x00020020 vaddr=0x3f400020 size=0x05d28 ( 23848) map
I (154) esp_image: segment 1: paddr=0x00025d50 vaddr=0x3ffb0000 size=0x020b0 ( 8368) load
I (157) esp_image: segment 2: paddr=0x00027e08 vaddr=0x40080000 size=0x00404 ( 1028) load
0x40080000: _WindowOverflow4 at /home/mali/esp/esp32/esp-idf-master/components/freertos/xtensa/xtensa_vectors.S:1730
I (162) esp_image: segment 3: paddr=0x00028214 vaddr=0x40080404 size=0x07e04 ( 32260) load
I (185) esp_image: segment 4: paddr=0x00030020 vaddr=0x400d0020 size=0x130d8 ( 78040) map
0x400d0020: _stext at ??:?
I (216) esp_image: segment 5: paddr=0x00043100 vaddr=0x40088208 size=0x01cc4 ( 7364) load
0x40088208: rtc_clk_cpu_freq_to_xtal at /home/mali/esp/esp32/esp-idf-master/components/soc/src/esp32/rtc_clk.c:431
I (226) boot: Loaded app from partition at offset 0x20000
I (226) boot: Checking flash encryption...
I (226) flash_encrypt: flash encryption is enabled (3 plaintext flashes left)
I (235) boot: Disabling RNG early entropy source...
I (241) cpu_start: Pro cpu up.
I (244) cpu_start: Application information:
I (249) cpu_start: Project name: hello-world
I (254) cpu_start: App version: v4.2-dirty
I (260) cpu_start: Compile time: Mar 4 2021 19:49:13
I (266) cpu_start: ELF file SHA256: 45b83567eb087450...
I (272) cpu_start: ESP-IDF: v4.2-dirty
I (277) cpu_start: Starting app cpu, entry point is 0x400815c0
0x400815c0: call_start_cpu1 at /home/mali/esp/esp32/esp-idf-master/components/esp32/cpu_start.c:287
I (0) cpu_start: App cpu up.
I (287) heap_init: Initializing. RAM available for dynamic allocation:
I (294) heap_init: At 3FFAE6E0 len 00001920 (6 KiB): DRAM
I (300) heap_init: At 3FFB28E0 len 0002D720 (181 KiB): DRAM
I (307) heap_init: At 3FFE0440 len 00003AE0 (14 KiB): D/IRAM
I (313) heap_init: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM
I (319) heap_init: At 40089ECC len 00016134 (88 KiB): IRAM
I (325) cpu_start: Pro cpu start user code
W (343) flash_encrypt: Flash encryption mode is DEVELOPMENT (not secure)
I (345) spi_flash: detected chip: generic
I (345) spi_flash: flash io: dio
W (349) spi_flash: Detected size(4096k) larger than the size in the binary image header(2048k). Using the size in the binary image header.
I (362) cpu_start: Starting scheduler on PRO CPU.
I (0) cpu_start: Starting scheduler on APP CPU.
Hello world!
This is esp32 chip with 2 CPU cores, WiFi/BT/BLE, silicon revision 1, 2MB external flash
Free heap: 299876
使能 flash 加密后，efuse 信息：
espefuse.py -p /dev/ttyUSB0 summary
Connecting....
Detecting chip type... ESP32
espefuse.py v3.0
EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value)
----------------------------------------------------------------------------------------
Calibration fuses:
BLK3_PART_RESERVE (BLOCK0): BLOCK3 partially served for ADC calibration data = False R/W (0b0)
ADC_VREF (BLOCK0): Voltage reference calibration = 1065 R/W (0b10101)
Config fuses:
XPD_SDIO_FORCE (BLOCK0): Ignore MTDI pin (GPIO12) for VDD_SDIO on reset = False R/W (0b0)
XPD_SDIO_REG (BLOCK0): If XPD_SDIO_FORCE, enable VDD_SDIO reg on reset = False R/W (0b0)
XPD_SDIO_TIEH (BLOCK0): If XPD_SDIO_FORCE & XPD_SDIO_REG = 1.8V R/W (0b0)
CLK8M_FREQ (BLOCK0): 8MHz clock freq override = 52 R/W (0x34)
SPI_PAD_CONFIG_CLK (BLOCK0): Override SD_CLK pad (GPIO6/SPICLK) = 0 R/W (0b00000)
SPI_PAD_CONFIG_Q (BLOCK0): Override SD_DATA_0 pad (GPIO7/SPIQ) = 0 R/W (0b00000)
SPI_PAD_CONFIG_D (BLOCK0): Override SD_DATA_1 pad (GPIO8/SPID) = 0 R/W (0b00000)
SPI_PAD_CONFIG_HD (BLOCK0): Override SD_DATA_2 pad (GPIO9/SPIHD) = 0 R/W (0b00000)
SPI_PAD_CONFIG_CS0 (BLOCK0): Override SD_CMD pad (GPIO11/SPICS0) = 0 R/W (0b00000)
DISABLE_SDIO_HOST (BLOCK0): Disable SDIO host = False R/W (0b0)
Efuse fuses:
WR_DIS (BLOCK0): Efuse write disable mask = 128 R/W (0x0080)
RD_DIS (BLOCK0): Efuse read disable mask = 1 R/W (0x1)
CODING_SCHEME (BLOCK0): Efuse variable block length scheme
= NONE (BLK1-3 len=256 bits) R/W (0b00)
KEY_STATUS (BLOCK0): Usage of efuse block 3 (reserved) = False R/W (0b0)
Identity fuses:
MAC (BLOCK0): Factory MAC Address
= c4:4f:33:7c:72:99 (CRC 0xfb OK) R/W
MAC_CRC (BLOCK0): CRC8 for factory MAC address = 251 R/W (0xfb)
CHIP_VER_REV1 (BLOCK0): Silicon Revision 1 = True R/W (0b1)
CHIP_VER_REV2 (BLOCK0): Silicon Revision 2 = False R/W (0b0)
CHIP_VERSION (BLOCK0): Reserved for future chip versions = 2 R/W (0b10)
CHIP_PACKAGE (BLOCK0): Chip package identifier = 0 R/W (0b000)
MAC_VERSION (BLOCK3): Version of the MAC field = 0 R/W (0x00)
Security fuses:
FLASH_CRYPT_CNT (BLOCK0): Flash encryption mode counter = 1 R/W (0b0000001)
UART_DOWNLOAD_DIS (BLOCK0): Disable UART download mode (ESP32 rev3 only) = False R/W (0b0)
FLASH_CRYPT_CONFIG (BLOCK0): Flash encryption config (key tweak bits) = 15 R/W (0xf)
CONSOLE_DEBUG_DISABLE (BLOCK0): Disable ROM BASIC interpreter fallback = True R/W (0b1)
ABS_DONE_0 (BLOCK0): Secure boot V1 is enabled for bootloader image = False R/W (0b0)
ABS_DONE_1 (BLOCK0): Secure boot V2 is enabled for bootloader image = False R/W (0b0)
JTAG_DISABLE (BLOCK0): Disable JTAG = True R/W (0b1)
DISABLE_DL_ENCRYPT (BLOCK0): Disable flash encryption in UART bootloader = False R/W (0b0)
DISABLE_DL_DECRYPT (BLOCK0): Disable flash decryption in UART bootloader = True R/W (0b1)
DISABLE_DL_CACHE (BLOCK0): Disable flash cache in UART bootloader = True R/W (0b1)
BLOCK1 (BLOCK1): Flash encryption key
= ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? -/-
BLOCK2 (BLOCK2): Secure boot key
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
BLOCK3 (BLOCK3): Variable Block 3
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
Flash voltage (VDD_SDIO) determined by GPIO12 on reset (High for 1.8V, Low/NC for 3.3V).
重新烧录 app.bin:
app_flash
idf.py app-flash monitor
esptool.py --chip esp32 -p /dev/ttyUSB0 -b 460800 --before=default_reset --after=no_reset write_flash --flash_mode dio --flash_freq 40m --flash_size 2MB 0x20000 hello-world.bin
--- idf_monitor on /dev/ttyUSB0 115200 ---
--- Quit: Ctrl+] | Menu: Ctrl+T | Help: Ctrl+T followed by Ctrl+H ---
ets Jun 8 2016 00:22:57
rst:0x1 (POWERON_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0xee
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:2
load:0x3fff0030,len:4
load:0x3fff0034,len:8988
load:0x40078000,len:15276
ho 0 tail 12 room 4
load:0x40080400,len:4568
0x40080400: _init at ??:?
entry 0x400806f4
I (31) boot: ESP-IDF v4.2-dirty 2nd stage bootloader
I (31) boot: compile time 19:49:22
I (31) boot: chip revision: 1
I (34) boot_comm: chip revision: 1, min. bootloader chip revision: 0
I (41) boot.esp32: SPI Speed : 40MHz
I (46) boot.esp32: SPI Mode : DIO
I (50) boot.esp32: SPI Flash Size : 2MB
I (55) boot: Enabling RNG early entropy source...
I (60) boot: Partition Table:
I (64) boot: ## Label Usage Type ST Offset Length
I (71) boot: 0 nvs WiFi data 01 02 00010000 00006000
I (79) boot: 1 phy_init RF data 01 01 00016000 00001000
I (86) boot: 2 factory factory app 00 00 00020000 00100000
I (94) boot: End of partition table
E (98) esp_image: image at 0x20000 has invalid magic byte
W (104) esp_image: image at 0x20000 has invalid SPI mode 209
W (110) esp_image: image at 0x20000 has invalid SPI size 14
E (116) boot: Factory app partition is not bootable
E (122) boot: No bootable app partitions in the partition table
encrypted-app-flash
idf.py encrypted-app-flash monitor
esptool.py --chip esp32 -p /dev/ttyUSB0 -b 460800 --before=default_reset --after=no_reset write_flash --flash_mode dio --flash_freq 40m --flash_size 2MB --encrypt 0x20000 hello-world.bin
--- idf_monitor on /dev/ttyUSB0 115200 ---
--- Quit: Ctrl+] | Menu: Ctrl+T | Help: Ctrl+T followed by Ctrl+H ---
ets Jun 8 2016 00:22:57
rst:0x1 (POWERON_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0xee
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:2
load:0x3fff0030,len:4
load:0x3fff0034,len:8988
load:0x40078000,len:15276
ho 0 tail 12 room 4
load:0x40080400,len:4568
0x40080400: _init at ??:?
entry 0x400806f4
I (31) boot: ESP-IDF v4.2-dirty 2nd stage bootloader
I (31) boot: compile time 19:49:22
I (31) boot: chip revision: 1
I (34) boot_comm: chip revision: 1, min. bootloader chip revision: 0
I (41) boot.esp32: SPI Speed : 40MHz
I (46) boot.esp32: SPI Mode : DIO
I (50) boot.esp32: SPI Flash Size : 2MB
I (55) boot: Enabling RNG early entropy source...
I (60) boot: Partition Table:
I (64) boot: ## Label Usage Type ST Offset Length
I (71) boot: 0 nvs WiFi data 01 02 00010000 00006000
I (79) boot: 1 phy_init RF data 01 01 00016000 00001000
I (86) boot: 2 factory factory app 00 00 00020000 00100000
I (94) boot: End of partition table
I (98) boot_comm: chip revision: 1, min. application chip revision: 0
I (105) esp_image: segment 0: paddr=0x00020020 vaddr=0x3f400020 size=0x05d28 ( 23848) map
I (123) esp_image: segment 1: paddr=0x00025d50 vaddr=0x3ffb0000 size=0x020b0 ( 8368) load
I (127) esp_image: segment 2: paddr=0x00027e08 vaddr=0x40080000 size=0x00404 ( 1028) load
0x40080000: _WindowOverflow4 at /home/mali/esp/esp32/esp-idf-master/components/freertos/xtensa/xtensa_vectors.S:1730
I (132) esp_image: segment 3: paddr=0x00028214 vaddr=0x40080404 size=0x07e04 ( 32260) load
I (155) esp_image: segment 4: paddr=0x00030020 vaddr=0x400d0020 size=0x130d8 ( 78040) map
0x400d0020: _stext at ??:?
I (186) esp_image: segment 5: paddr=0x00043100 vaddr=0x40088208 size=0x01cc4 ( 7364) load
0x40088208: rtc_clk_cpu_freq_to_xtal at /home/mali/esp/esp32/esp-idf-master/components/soc/src/esp32/rtc_clk.c:431
I (195) boot: Loaded app from partition at offset 0x20000
I (195) boot: Checking flash encryption...
I (195) flash_encrypt: flash encryption is enabled (3 plaintext flashes left)
I (205) boot: Disabling RNG early entropy source...
I (210) cpu_start: Pro cpu up.
I (214) cpu_start: Application information:
I (219) cpu_start: Project name: hello-world
I (224) cpu_start: App version: v4.2-dirty
I (229) cpu_start: Compile time: Mar 4 2021 19:49:13
I (235) cpu_start: ELF file SHA256: 45b83567eb087450...
I (241) cpu_start: ESP-IDF: v4.2-dirty
I (247) cpu_start: Starting app cpu, entry point is 0x400815c0
0x400815c0: call_start_cpu1 at /home/mali/esp/esp32/esp-idf-master/components/esp32/cpu_start.c:287
I (0) cpu_start: App cpu up.
I (257) heap_init: Initializing. RAM available for dynamic allocation:
I (264) heap_init: At 3FFAE6E0 len 00001920 (6 KiB): DRAM
I (270) heap_init: At 3FFB28E0 len 0002D720 (181 KiB): DRAM
I (276) heap_init: At 3FFE0440 len 00003AE0 (14 KiB): D/IRAM
I (283) heap_init: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM
I (289) heap_init: At 40089ECC len 00016134 (88 KiB): IRAM
I (295) cpu_start: Pro cpu start user code
W (312) flash_encrypt: Flash encryption mode is DEVELOPMENT (not secure)
I (314) spi_flash: detected chip: generic
I (315) spi_flash: flash io: dio
W (318) spi_flash: Detected size(4096k) larger than the size in the binary image header(2048k). Using the size in the binary image header.
I (331) cpu_start: Starting scheduler on PRO CPU.
I (0) cpu_start: Starting scheduler on APP CPU.
Hello world!
This is esp32 chip with 2 CPU cores, WiFi/BT/BLE, silicon revision 1, 2MB external flash
Free heap: 299876
espefuse.py -p /dev/ttyUSB0 summary
Connecting....
Detecting chip type... ESP32
espefuse.py v3.0
EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value)
----------------------------------------------------------------------------------------
Calibration fuses:
BLK3_PART_RESERVE (BLOCK0): BLOCK3 partially served for ADC calibration data = False R/W (0b0)
ADC_VREF (BLOCK0): Voltage reference calibration = 1065 R/W (0b10101)
Config fuses:
XPD_SDIO_FORCE (BLOCK0): Ignore MTDI pin (GPIO12) for VDD_SDIO on reset = False R/W (0b0)
XPD_SDIO_REG (BLOCK0): If XPD_SDIO_FORCE, enable VDD_SDIO reg on reset = False R/W (0b0)
XPD_SDIO_TIEH (BLOCK0): If XPD_SDIO_FORCE & XPD_SDIO_REG = 1.8V R/W (0b0)
CLK8M_FREQ (BLOCK0): 8MHz clock freq override = 52 R/W (0x34)
SPI_PAD_CONFIG_CLK (BLOCK0): Override SD_CLK pad (GPIO6/SPICLK) = 0 R/W (0b00000)
SPI_PAD_CONFIG_Q (BLOCK0): Override SD_DATA_0 pad (GPIO7/SPIQ) = 0 R/W (0b00000)
SPI_PAD_CONFIG_D (BLOCK0): Override SD_DATA_1 pad (GPIO8/SPID) = 0 R/W (0b00000)
SPI_PAD_CONFIG_HD (BLOCK0): Override SD_DATA_2 pad (GPIO9/SPIHD) = 0 R/W (0b00000)
SPI_PAD_CONFIG_CS0 (BLOCK0): Override SD_CMD pad (GPIO11/SPICS0) = 0 R/W (0b00000)
DISABLE_SDIO_HOST (BLOCK0): Disable SDIO host = False R/W (0b0)
Efuse fuses:
WR_DIS (BLOCK0): Efuse write disable mask = 128 R/W (0x0080)
RD_DIS (BLOCK0): Efuse read disable mask = 1 R/W (0x1)
CODING_SCHEME (BLOCK0): Efuse variable block length scheme
= NONE (BLK1-3 len=256 bits) R/W (0b00)
KEY_STATUS (BLOCK0): Usage of efuse block 3 (reserved) = False R/W (0b0)
Identity fuses:
MAC (BLOCK0): Factory MAC Address
= c4:4f:33:7c:72:99 (CRC 0xfb OK) R/W
MAC_CRC (BLOCK0): CRC8 for factory MAC address = 251 R/W (0xfb)
CHIP_VER_REV1 (BLOCK0): Silicon Revision 1 = True R/W (0b1)
CHIP_VER_REV2 (BLOCK0): Silicon Revision 2 = False R/W (0b0)
CHIP_VERSION (BLOCK0): Reserved for future chip versions = 2 R/W (0b10)
CHIP_PACKAGE (BLOCK0): Chip package identifier = 0 R/W (0b000)
MAC_VERSION (BLOCK3): Version of the MAC field = 0 R/W (0x00)
Security fuses:
FLASH_CRYPT_CNT (BLOCK0): Flash encryption mode counter = 1 R/W (0b0000001)
UART_DOWNLOAD_DIS (BLOCK0): Disable UART download mode (ESP32 rev3 only) = False R/W (0b0)
FLASH_CRYPT_CONFIG (BLOCK0): Flash encryption config (key tweak bits) = 15 R/W (0xf)
CONSOLE_DEBUG_DISABLE (BLOCK0): Disable ROM BASIC interpreter fallback = True R/W (0b1)
ABS_DONE_0 (BLOCK0): Secure boot V1 is enabled for bootloader image = False R/W (0b0)
ABS_DONE_1 (BLOCK0): Secure boot V2 is enabled for bootloader image = False R/W (0b0)
JTAG_DISABLE (BLOCK0): Disable JTAG = True R/W (0b1)
DISABLE_DL_ENCRYPT (BLOCK0): Disable flash encryption in UART bootloader = False R/W (0b0)
DISABLE_DL_DECRYPT (BLOCK0): Disable flash decryption in UART bootloader = True R/W (0b1)
DISABLE_DL_CACHE (BLOCK0): Disable flash cache in UART bootloader = True R/W (0b1)
BLOCK1 (BLOCK1): Flash encryption key
= ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? -/-
BLOCK2 (BLOCK2): Secure boot key
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
BLOCK3 (BLOCK3): Variable Block 3
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
Flash voltage (VDD_SDIO) determined by GPIO12 on reset (High for 1.8V, Low/NC for 3.3V).
2551
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