前言
今天是2023年10月05号,刚完成回湖南的假期,在这个竞争激烈的深圳,我希望大家都能和我一样天天保持旺盛的学习精神,我的心态很开放,只要不是公司机密,学习的东西我认为可以免费开放,收费就不叫学习,那叫买关键技术点(其实很多时候买了也用不好,还不如自己一步一个脚印的学习)。也希望大家支持紫光同创FPGA和SOCP系列产品线。
今天就讲讲例化,例化TOP是很多初学者不容易掌握的,除了我的这一篇,大家可以多看看别人写的这个通用知识点。希望国产芯片设计的越来越好,国外芯片也可以保持自己的特性共同发展。
建立一个工程
这次是以正点原子ZYNQ MPSOC ZU2CG开发板为例:
把主芯片加进去等等,生成一个 design_1的block design.
增加一个AXI GPIO的IP。
自动生成的代码
这个代码看着是不是很复杂,还每次修正都会变?
为什么呢?因为你的初始化顶层就是这个,要自己设计一个顶层并例化这个模块的时候到了。
自己设计TOP顶层架构
新建一个top.v
并大量修改代码如下:
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2023/10/04 12:19:24
// Design Name:
// Module Name: top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module top(
LED1_tri_o,//这些要用到的都要在TOP里定义好
sys_clk_p,//时钟定义好
sys_clk_n,
sys_rst_n,
led//测试LED定义好
);
output [0:0]LED1_tri_o;
wire [0:0]axi_gpio_0_GPIO_TRI_O;
wire [39:0]ps8_0_axi_periph_M00_AXI_ARADDR;
wire ps8_0_axi_periph_M00_AXI_ARREADY;
wire ps8_0_axi_periph_M00_AXI_ARVALID;
wire [39:0]ps8_0_axi_periph_M00_AXI_AWADDR;
wire ps8_0_axi_periph_M00_AXI_AWREADY;
wire ps8_0_axi_periph_M00_AXI_AWVALID;
wire ps8_0_axi_periph_M00_AXI_BREADY;
wire [1:0]ps8_0_axi_periph_M00_AXI_BRESP;
wire ps8_0_axi_periph_M00_AXI_BVALID;
wire [31:0]ps8_0_axi_periph_M00_AXI_RDATA;
wire ps8_0_axi_periph_M00_AXI_RREADY;
wire [1:0]ps8_0_axi_periph_M00_AXI_RRESP;
wire ps8_0_axi_periph_M00_AXI_RVALID;
wire [31:0]ps8_0_axi_periph_M00_AXI_WDATA;
wire ps8_0_axi_periph_M00_AXI_WREADY;
wire [3:0]ps8_0_axi_periph_M00_AXI_WSTRB;
wire ps8_0_axi_periph_M00_AXI_WVALID;
wire [0:0]rst_ps8_0_96M_peripheral_aresetn;
wire [39:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_ARADDR;
wire [1:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_ARBURST;
wire [3:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_ARCACHE;
wire [15:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_ARID;
wire [7:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_ARLEN;
wire zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_ARLOCK;
wire [2:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_ARPROT;
wire [3:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_ARQOS;
wire zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_ARREADY;
wire [2:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_ARSIZE;
wire zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_ARVALID;
wire [39:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_AWADDR;
wire [1:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_AWBURST;
wire [3:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_AWCACHE;
wire [15:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_AWID;
wire [7:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_AWLEN;
wire zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_AWLOCK;
wire [2:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_AWPROT;
wire [3:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_AWQOS;
wire zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_AWREADY;
wire [2:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_AWSIZE;
wire zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_AWVALID;
wire [15:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_BID;
wire zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_BREADY;
wire [1:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_BRESP;
wire zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_BVALID;
wire [31:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_RDATA;
wire [15:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_RID;
wire zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_RLAST;
wire zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_RREADY;
wire [1:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_RRESP;
wire zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_RVALID;
wire [31:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_WDATA;
wire zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_WLAST;
wire zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_WREADY;
wire [3:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_WSTRB;
wire zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_WVALID;
wire zynq_ultra_ps_e_0_pl_clk0;
wire zynq_ultra_ps_e_0_pl_resetn0;
assign LED1_tri_o[0] = axi_gpio_0_GPIO_TRI_O;
input sys_clk_p;
input sys_clk_n;
input sys_rst_n;
output [1:0]led;
design_1 design_1_wrapper**//例化刚才一直在变的这个block**
(
.LED1_tri_o(LED1_tri_o)
);
led_twinkle led_twinkle_wrapper**//例化LED闪烁的IP**
(
.sys_clk_p(sys_clk_p),
.sys_clk_n(sys_clk_n),
.sys_rst_n(sys_rst_n),
.led(led)
);
endmodule
设计一下约束
#IO管脚约束
#时钟周期约束
create_clock -name sys_clk_p -period 10 [get_ports sys_clk_p]
#时钟管脚
set_property IOSTANDARD DIFF_HSTL_I_12 [get_ports sys_clk_p]
set_property IOSTANDARD DIFF_HSTL_I_12 [get_ports sys_clk_n]
set_property PACKAGE_PIN AE5 [get_ports sys_clk_p]
set_property PACKAGE_PIN AF5 [get_ports sys_clk_n]
#复位管脚
set_property -dict {PACKAGE_PIN AH11 IOSTANDARD LVCMOS33} [get_ports sys_rst_n]
#LED灯
set_property -dict {PACKAGE_PIN AE10 IOSTANDARD LVCMOS33} [get_ports {led[0]}]
set_property -dict {PACKAGE_PIN AF10 IOSTANDARD LVCMOS33} [get_ports {led[1]}]
set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS33} [get_ports {LED1_tri_o[0]}]
代码中LED闪灯的程序led_twinkle.v—这个是正点原子的测试例程。
`timescale 1ns / 1ps
//Copyright ©***********************************//
//原子哥在线教学平台:www.yuanzige.com
//技术支持:www.openedv.com
//淘宝店铺:http://openedv.taobao.com
//关注微信公众平台微信号:“正点原子”,免费获取ZYNQ & FPGA & STM32 & LINUX资料。
//版权所有,盗版必究。
//Copyright© 正点原子 2018-2028
//All rights reserved
//----------------------------------------------------------------------------------------
// File name: led_twinkle
// Last modified Date: 2021/10/13 10:55:56
// Last Version: V1.0
// Descriptions: LED灯闪烁
//----------------------------------------------------------------------------------------
// Created by: 正点原子
// Created date: 2021/10/13 10:55:56
// Version: V1.0
// Descriptions: The original version
//
//----------------------------------------------------------------------------------------
//************************************************//
module led_twinkle(
input sys_clk_p , //系统差分输入时钟
input sys_clk_n , //系统差分输入时钟
input sys_rst_n, //系统复位,低电平有效
output [1:0] led //LED灯
);
//reg define
reg [26:0] cnt ;
//*****************************************************
//** main code
//*****************************************************
//对计数器的值进行判断,以输出LED的状态
assign led = (cnt < 27’d5000_0000) ? 2’b01 : 2’b10 ;
//assign led = (cnt < 27’d5) ? 2’b01 : 2’b10 ; //仅用于仿真
//转换差分信号
IBUFDS diff_clock
(
.I (sys_clk_p), //系统差分输入时钟
.IB(sys_clk_n), //系统差分输入时钟
.O (sys_clk) //输出系统时钟
);
//计数器在0~10000_0000之间进行计数
always @ (posedge sys_clk or negedge sys_rst_n) begin
if(!sys_rst_n)
cnt <= 27’d0;
else if(cnt < 27’d10000_0000)
//else if(cnt < 27’d10) //仅用于仿真
cnt <= cnt + 1’b1;
else
cnt <= 27’d0;
end
endmodule
看看效果吧,一闪一闪,你再加IP就不会变动到TOP了。加油。