如何给Vref加约束

原文链接https://forums.xilinx.com/t5/Other-FPGA-Architecture/help-me-constraints-external-Vref/td-p/736905

If you use an I/O standard that needs the VREF (an SSTL, HSTL, etc… input), then the tools will know that a VREF is necessary. If you use the internal VREF for the bank that those I/O are in, using

set_property INTERNAL_VREF [get_banks ]

then it will know that the VREF pins are not needed to provide the VREF. In this case, or in the case where you use no I/Os that need VREF, the VREF pins (which are dual purpose) can be used as regular I/O.

If you use an I/O that needs a VREF, and you don’t set the INTERNAL_VREF on the bank, then all the VREF pins in that bank must be connected to the correct VREF voltage on the board. There is nothing you need to tell the tools - they simply assume it. If, however, you try and set the PACKA