FPGA 学习10 状态机的理解

FPGA 学习10 状态机的理解

Hello.v 文件

module Hello(Clk,Rst_n,data,led);

	input Clk;//50M
	input Rst_n;//低电平复位
	
	input [7:0]data;
	
	output reg led;
	
	localparam
		CHECK_H	= 5'b0_0001,
		CHECK_e 	= 5'b0_0010,
		CHECK_la	= 5'b0_0100,
		CHECK_lb	= 5'b0_1000,
		CHECK_o	= 5'b1_0000;

	reg[4:0]state;
	
	always@(posedge Clk or negedge Rst_n)
	if(!Rst_n)begin
		led <= 1'b1;
		state <= CHECK_H;
	end
	else begin
		case(state)
			CHECK_H:
				if(data == "H") 
					state <= CHECK_e;
				else
					state <= CHECK_H;
			
			CHECK_e:
				if(data == "e")
					state <= CHECK_la;
				else
					state <= CHECK_H;
					
			CHECK_la:
				if(data == "l")
					state <= CHECK_lb;
				else
					state <= CHECK_H;
					
			CHECK_lb:
				if(data == "l")
					state <= CHECK_o;
				else	
					state <= CHECK_H;
					
			CHECK_o:
				begin
					state <= CHECK_H;
					if(data == "o")
						led <= ~led;
					else
						led <= led;
				end
				
			default:state <= CHECK_H;
		endcase		
	end

endmodule
	
	/*				
			CHECK_o :				//进入第5个状态条件
				if(data == "o") begin
					led <= ~led ;
					state <= CHECK_H ;

				end	
				else
					state <= CHECK_H ;	
			default :				//其它非正常状态
					state <= CHECK_H ;
	*/

Hello_tb.v 文件

`timescale 1ns/1ns
`define clock_period 20
module Hello_tb ;

	reg Clk ;
	reg Rst_n ;
	reg [7:0]ASCII;
	
	wire led;

	Hello Hello_0(
		.Clk(Clk) ,
		.Rst_n(Rst_n) ,
		.data(ASCII) ,
		
		.led(led) 
	);

	initial Clk = 1 ;
	always#(`clock_period/2) Clk = ~Clk ;
	
	initial begin
	//信号初始化
		Rst_n = 0;
		ASCII = 0;
		#(`clock_period * 200);
		Rst_n = 1;
		#(`clock_period * 200 +1);
		
		
	// forever : 循环调用，在仿真的时候设置仿真时间即可
		forever begin
			ASCII = "I";
			#(`clock_period);
			ASCII = "A";
			#(`clock_period);
			ASCII = "M";
			#(`clock_period);
			ASCII = "X";
			#(`clock_period);
			ASCII = "i";
			#(`clock_period);
			ASCII = "a";
			#(`clock_period);
			ASCII = "o";	
			#(`clock_period);
			ASCII = "M";
			#(`clock_period);
			ASCII = "e";
			#(`clock_period);
			ASCII = "i";
			#(`clock_period);
			ASCII = "g";
			#(`clock_period);
			ASCII = "e";	
			
			#(`clock_period);
			ASCII = "H";
			#(`clock_period);
			ASCII = "E";
			
			#(`clock_period);
			ASCII = "M";
			#(`clock_period);
			ASCII = "l";
			
			#(`clock_period);
			ASCII = "H";
			#(`clock_period);
			ASCII = "E";
			#(`clock_period);
			ASCII = "L";
			#(`clock_period);
			ASCII = "L";
			#(`clock_period);
			ASCII = "O";
			#(`clock_period);
			
			ASCII = "H";
			#(`clock_period);
			ASCII = "e";
			#(`clock_period);
			ASCII = "l";
			#(`clock_period);
			ASCII = "l";
			#(`clock_period);
			ASCII = "o";
			
			#(`clock_period);
			ASCII = "l";
		end
	end
		
endmodule