参考文章:
http://hi.baidu.com/282280072/blog/item/ff8d88c36502302de4dd3b3c.html
花了我好几天,终于把Quartus II时序仿真给解决了。
在仿真时,总是遇到一个奇怪的错误.
vsim -voptargs=+acc work_test.tb # vsim -voptargs=+acc work_test.tb # Loading work_test.tb # Loading work_test.test # Loading work_test.cycloneii_io # Loading work_test.cycloneii_mux21 # Loading work_test.cycloneii_dffe # Loading work_test.cycloneii_asynch_io # Loading work_test.cycloneii_lcell_comb # Loading work_test.cycloneii_lcell_ff # ** INTERNAL ERROR: mtiarOpen(): Unrecognized file path (test_v_fast.sdo) # ** Error: (vsim-SDF-3894) test_v_fast.sdo: Compiled SDF file was not found. # Loading work_test.CYCLONEII_PRIM_DFFE # ** Error: (vsim-7) Failed to open SDF file "test_v_fast.sdo" in read mode. # No such file or directory. (errno = ENOENT) # ** Error: (vsim-SDF-3445) Failed to parse SDF file "test_v_fast.sdo". # Time: 0 ps Iteration: 0 Instance: /tb File: E:/test/simulation/modelsim/tb.v # Error loading design
终于,我在网上到了解决的办法。华清远见的视频教程中,授课老师认为这是ModelSim软件本身的问题。
提供的解决办法是:新建Project。把除sdf文件以外的文件添加到工程编译。然后打开start simulation对话框,选design页,选中testbench文件,再点开sdf页,添加sdf文件,选中左下角的两个选项(禁止警告,把错误变成警告)。继续仿真即可。
详细可以看视频教程.
测试代码如下:
`timescale 1ns/1ns module tb; reg clk; reg rst; wire div; test u1( .clk(clk), .rst(rst), .div(div) ); initial begin clk=0; forever #10 clk=~clk; end initial begin rst=0; #1000 rst=1; #1000 stop; end endmodule