FPGA的PLL倍频

 

配置就不用说了，看“PLL配置详细说明.pdf”即可。

测试文件如下：

 

`timescale 1 ns/ 1 ns
module PLL100_vlg_tst();
     

reg eachvec;

reg areset;
reg inclk0;
                                         
wire c0;
wire locked;

                    
PLL100 i1 (
 .areset(areset),
 .c0(c0),
 .inclk0(inclk0),
 .locked(locked)
);

initial                                               
begin                                                 
                                        
$display("Running testbench");                      
end

initial
  begin
 inclk0=0;
    forever #12.5 inclk0=~inclk0; 
  end
 
 
 initial
   begin
     areset=0;
 #1000  areset=1;  
    #2000  areset=0;
 #3000 $stop;
   end
                                                  
always                                                
               
begin                                                 
                      
@eachvec;                                             
                                        
end                                                   
endmodule

 结果如下：