VHDL+LED控制器+50MHZ分频+例化

题目：设计一个LED控制器，能够控制LED以不同速度闪烁，具体要求如下：
要求：开关SW1做为多路输入端，当开关为高电平‘1’时，LED以1秒间隔闪烁（亮0.5秒，灭0.5秒循环往复）。当开关为低电平‘0’时，LED以10秒间隔闪烁（亮5秒，灭5秒循环往复）。

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思路

先分别写出分频器，计数器，选择器，然后例化3个器件

提示：以下是本篇文章正文内容，下面案例可供参考

一、必要器件

1.分频器

代码如下（示例）：

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fenpin is
	port (clk50m:in std_logic;
			clk:out std_logic);
end entity;

architecture fen of fenpin is
signal cnt: integer range 0 to 24999999; 
signal clkout :std_logic;
begin
	process(clk50m)
	begin
	if clk50m'event and clk50m = '1' then
		if cnt = 24999999 then
			cnt <= 0;
			clkout <= not clkout;
		else
			cnt <= cnt + 1;
	end if;
	end if;
	end process;
	clk <= clkout;
end architecture;

2.计数器

代码如下（示例）：

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity count is
port(clk1,rst:in std_logic;
		clk10: out std_logic);
end count;
architecture count10 of count is
signal cnt:integer range 0 to 4; 
signal clkout :std_logic;
begin
	process(clk1)
	begin 
	if rst='1' then 
		cnt<=0;
	elsif rising_edge(clk1) then
		if cnt = 4 then
			cnt<= 0;
			clkout <= not clkout;
		else 
			cnt<=cnt+1;
		end if;
	end if;
	end process;
	clk10<=clkout;
end count10;

3.选择器

代码如下（示例）：

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mux is
port (sw :in std_logic;
		clk1:in std_logic;
		clk10:in std_logic;
		clkout:out std_logic);
end mux;
architecture mux21 of mux is
begin
	process(sw ,clk1,clk10)
	begin
	if sw='1' then 
		clkout<= clk1;
	else
		clkout<= clk10;
	end if;
	end process;
end mux21;

二、元件例化设计顶层

代码如下（示例）：

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity leds is
port(clki,SW:in std_logic;
		clko:out std_logic);
end leds;
architecture led of leds is
signal u1,u2:std_logic;
component fenpin is
	port (clk50m:in std_logic;
			clk:out std_logic);
end component;
component count is
	port(clk1,rst:in std_logic;
		clk10: out std_logic);
end component;
component mux is
	port (sw :in std_logic;
			clk1:in std_logic;
			clk10:in std_logic;
			clkout:out std_logic);
end component;
begin
	fen:fenpin port map(clki,u1);
	cnt:count port map(u1,'0',u2);
	m:mux port map(SW,u1,u2,clko);
end led;