目录
1. Assignment operators(赋值操作符)
2. Operations on logic and bit type
3. Wild equality and inequality
4. Operator precddence and associativity
摘要:SV的操作符是verilog和c语言的集合;
1. Assignment operators(赋值操作符)
- =
- +=
- -=
- *=
- /=
- %=
- &=
- |=
- ^=
- <<=
- >>=
- <<<=
- >>>=
赋值操作符在语义上等同于阻塞赋值,任何操作符左边的表达式只计算一次;
例子:
1 module assignment_operator ();
2
3 reg [31:0] a = 100;
4
5 initial begin
6 $display (" a := %h", a );
7 a += 4;
8 $display (" a += 4 := %h", a );
9 a -= 4;
10 $display (" a -= 4 := %h", a );
11 a *= 4;
12 $display (" a *= 4 := %h", a );
13 a /= 4;
14 $display (" a /= 4 := %h", a );
15 a %= 17;
16 $display (" a %s= 17 := %h", "%", a );
17 a &= 16'hFFFF;
18 $display (" a &= 16'hFFFF := %h", a );
19 a |= 16'hFFFF;
20 $display (" a |= 16'hFFFF := %h", a );
21 a ^= 16'hAAAA;
22 $display (" a ^= 16h'AAAA := %h", a );
23 a <<= 4;
24 $display (" a <<= 4 := %h", a );
25 a >>= 4;
26 $display (" a >>= 4 := %h", a );
27 a <<<= 14;
28 $display (" a <<<= 14 := %h", a );
29 a >>>= 14;
30 $display (" a >>>= 14 := %h", a );
31 #1 $finish;
32 end
33
34 endmodule
35
36 //compile result
37
38 a := 00000064
39 a += 4 := 00000068
40 a -= 4 := 00000064
41 a *= 4 := 00000190
42 a /= 4 := 00000064
43 a %= 17 := 0000000f
44 a &= 16'hFFFF := 0000000f
45 a |= 16'hFFFF := 0000ffff
46 a ^= 16h'AAAA := 00005555
47 a <<= 4 := 00055550
48 a >>= 4 := 00005555
49 a <<<= 14 := 15554000
50 a >>>= 14 := 00005555
2. Operations on logic and bit type
- 一个操作数是bit类型,另一个操作数是logic类型,则结果为logic类型;
- 一个操作数是int类型,另一个操作数是integer类型,则结果为integer类型;
- 对于操作符!= 和 == ,如果其中一个操作符包含x或者z,则返回x;
例子:
1 module bit_logic_operator ();
2
3 bit [7:0] a = 8'b01xz_01xz;
4 logic [7:0] b = 8'b01xz_01xz;
5 integer c = 32'b01xz_01xz_01xz_01xz;
6 int d = 32'b01xz_01xz_01xz_01xz;
7
8 initial begin
9 $display ("Value of bit a = %b", a);
10 $display ("Value of logic b = %b", b);
11 $display ("Value of integer c = %b", c);
12 $display ("Value of int d = %b", d);
13 $display (" bit + integer = %b", a + c);
14 $display (" logic + int = %b", b + d);
15 a = 10;
16 b = 20;
17 c = 30;
18 d = 40;
19 $display (" bit + logic = %b", a + b);
20 $display (" integer + int = %b", c + d);
21 end
22
23 endmodule
24
25 //compile result
26
27 Value of bit a = 01000100
28 Value of logic b = 01xz01xz
29 Value of integer c = 000000000000000001xz01xz01xz01xz
30 Value of int d = 00000000000000000100010001000100
31 bit + integer = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
32 logic + int = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
33 bit + logic = 00011110
34 integer + int = 00000000000000000000000001000110
3. Wild equality and inequality
- Wild equality operator (=?=)和 (!?=) 将x和z当做统配符做处理;
- 通配符:通配符可匹配任意0,1,z,x;
例子:
1 module wild_equality_operator ();
2
3 bit [7:0] data = 8'hFF;
4
5 initial begin
6 // Compare with wild equality
7 if (data =?= 8'b1xxx_z1xz) begin
8 $display ("Data %b matches with %b", data, 8'b1xxx_z1xz);
9 end
10 // Compare with wild non-equality
11 if (data !?= 8'b1xxx_z1x0) begin
12 $display ("Data %b does not matches with %b", data, 8'b1xxx_z1x0);
13 end
14 #1 $finish;
15 end
16
17 endmodule
18
19 //compile result
20
21 Data 11111111 matches with 1xxxz1xz
22 Data 11111111 does not matches with 1xxxz1x0
4. Operator precddence and associativity
Operators | Precedence |
() [] :: . | left |
+ - ! ~ & ~& | ~| ^ ~^ ^~ ++ -- unary | right |
** | left |
* / % | left |
+ - (binary) | left |
<< >> <<< >>> | left |
< <= > >= inside dist | left |
== != === !== =?= !?= | left |
& (binary) | left |
^ ~^ ^~ (binary) | left |
| (binary) | left |
&& | left |
|| | left |
? : (conditional operator) | right |
> | right |
= += -= *= /= %= &= ^= |= <<= >>= <<<= >>>= := :/ <= | none |
{} {{}} | concatenation |
5. Concatenation
- {a,b}用于连接a,b两个元素;a和b可以是表达式;
- {a,b}也可以用于对数组赋值;
- 也可以和复制操作符配合使用,如:{a,3{b}}
例子:
1 module struct_expr_operator();
2
3 typedef struct {
4 int x;
5 int y;
6 } myStruct;
7
8 myStruct s1;
9 int k = 1;
10
11 initial begin
12 #1 s1 = '{1, 2+k};
13 // by position
14 #1 $display("Value of x = %g y = %g by position", s1.x, s1.y);
15 #1 s1 = '{x:2, y:3+k};
16 // by name
17 #1 $display("Value of s1 ", s1, " by name");
18 #1 $finish;
19 end
20
21 endmodule
22
23 //compile result
24
25 Value of x = 1 y = 3 by position
26 Value of s1 2 4 by name
6. Streaming operators
- 流操作符(stream)是将位流类型按用户指定的顺序打包成一个位序列;
- 在左侧使用时,流操作符执行相反的操作,将位流解包到一个或多个变量中;
1 module streaming();
2
3 //-------------------------------
4 // PACK Example
5 //-------------------------------
6 int j = { "A", "B", "C", "D" };
7
8 bit [31:0] stream;
9
10 initial begin
11 $display(" PACK");
12 $display("Value of j %0x",j);
13 $monitor("@%0dns stream value is %x",$time, stream);
14 #1 stream = { << byte {j}};
15 #1 stream = { >> {j}} ;
16 #1 stream = { << { 8'b0011_0101 }};
17 #1 stream = { << 16 {j}};
18 #1 stream = { << 4 { 6'b11_0101 }};
19 #1 stream = { >> 4 { 6'b11_0101 }} ;
20 #1 stream = { << 2 { { << { 4'b1101 }} }};
21 end
22
23 //-------------------------------
24 // UNPACK Example
25 //-------------------------------
26 int a, b, c;
27 logic [10:0] up [3:0];
28 logic [11:1] p1, p2, p3, p4;
29 bit [96:1] y;
30 int j ;
31 bit [99:0] d;
32
33 initial begin
34 #20;
35 $display(" UNPACK");
36 // Below line should give compile error
37 //{>>{ a, b, c }} = 23'b1;
38 {>>{ a, b, c }} = 96'b1;
39 $display("@%0dns a %x b %x c %x",$time,a,b,c);
40 {>>{ a, b, c }} = 100'b1;
41 $display("@%0dns a %x b %x c %x",$time,a,b,c);
42 { >> {p1, p2, p3, p4}} = up;
43 $display("@%0dns p1 %x p2 %x p3 %x p4 %x",$time,p1,p2,p3,p4);
44 y = {>>{ a, b, c }};
45 $display("@%0dns y %x",$time,y);
46 // Below line should give compile error
47 //j = {>>{ a, b, c }};
48 d = {>>{ a, b, c }};
49 $display("@%0dns d %x",$time,d);
50 end
51
52 endmodule
53
54 //compile result
55
56 PACK
57 Value of j 41424344
58 @0ns stream value is 00000000
59 @1ns stream value is 44434241
60 @2ns stream value is 41424344
61 @3ns stream value is 000000ac
62 @4ns stream value is 43444142
63 @5ns stream value is 0000004d
64 @6ns stream value is d4000000
65 @7ns stream value is 0000000e
66 UNPACK
67 @20ns a 00000000 b 00000000 c 00000001
68 @20ns a 00000000 b 00000000 c 00000000
69 @20ns p1 xxx p2 xxx p3 xxx p4 xxx
70 @20ns y 000000000000000000000000
71 @20ns d 0000000000000000000000000
7. set membership
- SV支持单值和集合集成员的操作;
- 遍历数组进行查找;
1 //语法
2 inside_expression ::= expression inside { open_range_list }
例子:
1 module set_member();
2
3 int array [$] = {1,2,3,4,5,6,7};
4 int check = 0;
5
6 initial begin
7 if (check inside {array}) begin
8 $display("check is inside array");
9 end else begin
10 $display("check is not inside array");
11 end
12 check = 5;
13 if (check inside {array}) begin
14 $display("check is inside array");
15 end else begin
16 $display("check is not inside array");
17 end
18 check = 1;
19 // Constant range
20 if (check inside {[0:10]}) begin
21 $display("check is inside array");
22 end else begin
23 $display("check is not inside array");
24 end
25
26 end
27
28 endmodule
29
30 //compile result
31
32 check is not inside array
33 check is inside array
34 check is inside array