07 1pps上升沿判断

延时一个时钟是不稳定的，有毛刺时上升沿判断就会出错。

1、.v文件

module _1pps_up_judge(
     input  sys_clk_50M,
     input  sys_rst_n  ,
     input  uart_1pps  ,
     
     output  uart_1pps_up
    );
    
    wire uart_1pps_up;
    
    //抓取上升沿，给出一个脉冲信号
    assign uart_1pps_up=uart_1pps_1&&(~uart_1pps_2)&&(~uart_1pps_3)&&(~uart_1pps_4)&&(~uart_1pps_5)&&(~uart_1pps_6);
    
     //定义6个寄存器
    reg uart_1pps_1;
    reg uart_1pps_2;  //2比1晚一个时钟周期
    reg uart_1pps_3;
    reg uart_1pps_4;
    reg uart_1pps_5;
    reg uart_1pps_6;
    
    always @(posedge sys_clk_50M)begin
         if(!sys_rst_n)begin
            uart_1pps_1<=1'b0;
            uart_1pps_2<=1'b0;
            uart_1pps_3<=1'b0;
            uart_1pps_4<=1'b0;
            uart_1pps_5<=1'b0;
            uart_1pps_6<=1'b0;
         end
         else begin
            uart_1pps_1<=uart_1pps;
            uart_1pps_2<=uart_1pps_1;
            uart_1pps_3<=uart_1pps_2;
            uart_1pps_4<=uart_1pps_3;
            uart_1pps_5<=uart_1pps_4;
            uart_1pps_6<=uart_1pps_5;
         end
    end
    
endmodule

2、.tb仿真代码

`timescale 1ns / 1ps



module tb_01_1pps_up_judge( );
    reg sys_clk_50M;
    reg sys_rst_n;
    reg uart_1pps;
    
    wire uart_1pps_up;
    
    _1pps_up_judge _1pps_up_judge_u(
       .sys_clk_50M   (sys_clk_50M  ),
       .sys_rst_n     (sys_rst_n    ),
       .uart_1pps     (uart_1pps    ),
                    
       . uart_1pps_up ( uart_1pps_up)
       );            
    
    
initial begin
    sys_clk_50M=1'b0;
    sys_rst_n=1'b0;
    uart_1pps=1'b0;
    
    #100   sys_rst_n=1'b1;  //延时100ns后复位
    
    #100  uart_1pps=1'b1;   //秒脉冲上升沿到达
    
    #500  uart_1pps=1'b0;   //秒脉冲高电平持续500ns
    
    
end


always #10 sys_clk_50M=~sys_clk_50M;  //使用always 语句对时钟进行赋值，周期为20ns，频率50MHz



endmodule

3、仿真波形