1.逻辑电路
2.端口
3.VHDL语言
3.1使用并行语句
library ieee;
use ieee.std_logic_1164.all;
entity mux21 is
port(
a,b,s:in bit;
q:out bit
);
end mux21;
architecture mux of mux21 is
begin
q <= a when s ='0'
else b;
end mux;
3.2使用布尔方程表达式
architecture mux of mux21 is
begin
q<=(a and (not s))or(b and s);
end mux;
3.3使用顺序语句
architecture mux of mux21 is
begin
process(a,b,s)
if s='0'then
q<=a;
else
q<=b;
end if;
end process;
end mux;