---------------------二选一数据选择器 底层文件-------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.ALL;
ENTITY MUX IS
PORT (
A, B, S : IN STD_LOGIC;
Y : OUT STD_LOGIC
);
END MUX;
ARCHITECTURE ART1 OF MUX IS
BEGIN
Y <= A WHEN S = '0' ELSE
B;
END ART1; -- ART1
---------------------VHDL 主文件-------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.std_logic_unsigned.ALL;
ENTITY LED IS
GENERIC (LIMIT : INTEGER := 255);
PORT (
sys_clk : IN STD_LOGIC;
--sys_rst_n : OUT STD_LOGIC;
MY_LED : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
MY_KEY : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
BOARD_LED_RED : OUT STD_LOGIC;
BOARD_LED_GREEN : OUT STD_LOGIC;
BOARD_LED_BLUE : OUT STD_LOGIC;
------------四选一数据选择器---------------
D0, D1, D2, D3 : IN STD_LOGIC;
S0, S1 : IN STD_LOGIC;
Y : OUT STD_LOGIC
);
END ENTITY LED;
ARCHITECTURE BEV OF LED IS
SIGNAL buff : BIT_VECTOR(7 DOWNTO 0) := "11111110";
SIGNAL CLK_Counter : INTEGER := 0;
SIGNAL MY_CLK : STD_LOGIC := '0';
SIGNAL A, B : STD_LOGIC;
CONSTANT TIME_1s : INTEGER := 24000000; ---1s
CONSTANT TIME_05s : INTEGER := 12000000; ---0.5s
----------------------上升沿函数------------------------------
FUNCTION positive_edge(SIGNAL s : STD_LOGIC) RETURN BOOLEAN IS
BEGIN
RETURN(s'event AND s = '1');
END FUNCTION positive_edge;
----------------------下降沿函数------------------------------
FUNCTION falling_edge(SIGNAL s : STD_LOGIC) RETURN BOOLEAN IS
BEGIN
RETURN(s'event AND s = '0');
END FUNCTION falling_edge;
---------------------元件例化---------------------------------
COMPONENT MUX IS
PORT (
A, B, S : IN STD_LOGIC;
Y : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
U1 : MUX PORT MAP(D0, D1, S0, A);
U2 : MUX PORT MAP(A => D2, B => D3, S => S0, Y => B);
U3 : MUX PORT MAP(A, B, S1, Y => Y);
END ARCHITECTURE BEV;
VHDL 四选一数据选择器
最新推荐文章于 2022-04-22 19:26:46 发布