Verilog Hdl实现二十四小时计时

根据之前讨论过的计数器分频CSDN，以及共阳极七段数码管CSDN，下面研究在50MHz晶振下，六个数码管实现24小时计时功能。

50MHz基准时间单位：

clk_50:        50MHz=5×Hz=20ns

要实现二十四小时时钟：则要分别实现1s、1min、10min、1h、10h的基准单位以及对24整点的界定

具体实现代码：

module	jishi_24
			    (
					clk,
					rst,
					pause,
					led0,
					led1,
					led2,
					led3,
					led4,
					led5
				);

//************************输入输出*************************//

//input:
	input			clk;
	input			rst;
	input			pause;
	
//output:
	output [6:0]	led0;
	output [6:0]	led1;
	output [6:0]	led2;
	output [6:0]	led3;
	output [6:0]	led4;
	output [6:0]	led5;
	
//************************参数定义*************************//

		

//************************变量定义*************************//

//regs:
	reg 			clk0;
	reg 			clk1;
	reg 			clk2;
	reg 			clk3;
	reg 			clk4;
	reg 			clk5;
	reg [24:0]		cnt;
	reg [3:0]		cnt0;
	reg [3:0]		cnt1;
	reg [3:0]		cnt2;
	reg [3:0]		cnt3;
	reg [3:0]		cnt4;
	reg [3:0]		cnt5;
	reg [6:0]		led0;
	reg [6:0]		led1;
	reg [6:0]		led2;
	reg [6:0]		led3;
	reg [6:0]		led4;
	reg [6:0]		led5;

//************************程序定义*************************//
//二十四小时计时

//20ns->1s:5000_0000
//标准偶数分频
always @(posedge clk or negedge rst)
begin
    if(~rst)//复位键
		begin
			cnt <= 1'b0;
			clk0 <= 1'b0;
		end
    else if(cnt == 25'd2499_9999)//5000_0000/2 - 1
		begin
			cnt <= 1'b0; 
			clk0 <= ~clk0;//1s
		end
	else if(pause)//暂停键
			cnt <= cnt+1'b0;
    else 
			cnt <= cnt+1'b1;
end


//1s->10s:10
//半周期偶数分频
always @(posedge clk0 or negedge rst)
begin
    if(~rst)
		begin
			cnt0 <= 1'b0;
			clk1 <= 1'b0;
		end
	else if(cnt0 == 4'b1001)//10:0~9
		begin
			cnt0 <= 1'b0;
			clk1 <= ~clk1;//10s
		end
    else 
		begin
			cnt0 <= cnt0+1'b1;
			clk1 <= 1'b0;
		end
end


//10s->1min:6
always @(posedge clk1 or negedge rst)
begin
    if(~rst)
		begin
            cnt1 <= 1'b0;
			clk2 <= 1'b0;
		end
    else if(cnt1 == 4'b0101)//6:0~5
		begin
            cnt1 <= 1'b0;
			clk2 <= ~clk2;//1min
		end
    else 
		begin
			cnt1 <= cnt1+1'b1;
			clk2 <= 1'b0;
		end
end


//1min->10min:10
always@(posedge clk2 or negedge rst)
begin
    if(~rst)
		begin
            cnt2 <= 1'b0;
			clk3 <= 1'b0;
		end
    else if(cnt2 == 4'b1001)//10:0~9
		begin
            cnt2 <= 1'b0;
			clk3 <= ~clk3;//10min
		end
    else
		begin
		    cnt2 <= cnt2+1'b1;
			clk3 <= 1'b0;
		end
end


//10min->1h:6
always @(posedge clk3 or negedge rst)
begin
    if(~rst)
		begin
            cnt3 <= 1'b0;
			clk4 <= 1'b0;
		end
    else if(cnt3 == 4'b0101)//6:0~5
		begin
            cnt3 <= 1'b0;
			clk4 <= ~clk4;
		end
    else 
		begin
		    cnt3 <= cnt3+1'b1;
			clk4 <= 1'b0;
		end
end



//1h->10h:10
always @(posedge clk4 or negedge rst)
begin
    if(~rst)
		begin
            cnt4 <= 1'b0;
			clk5 <= 1'b0;
		end
    else if(cnt4 == 4'b1001)//10:0~9
		begin
            cnt4 <= 1'b0;
			clk5 <= ~clk5;
		end
	else if(cnt5 == 4'b0010 & cnt4 == 4'b0011)//23
		begin
			cnt4 <= 1'b0;
			clk5 <= ~clk5;
		end
    else 
		begin
		    cnt4 <= cnt4+1'b1;
			clk5 <= 1'b0;
		end
end


//24h
always @(posedge clk5 or negedge rst)
begin
    if(~rst)
            cnt5 <= 1'b0;
    else if(cnt5 == 4'b0010)//24h
            cnt5 <= 1'b0;
    else 
		    cnt5 <= cnt5+1'b1;
end



//1s数码管
always@(cnt0)
begin
	case (cnt0)
		4'd0:	 led0 <= 7'b100_0000;//0 
		4'd1:	 led0 <= 7'b111_1001;//1 		
		4'd2: 	 led0 <= 7'b010_0100;//2								
		4'd3: 	 led0 <= 7'b011_0000;//3		
		4'd4: 	 led0 <= 7'b001_1001;//4								
		4'd5: 	 led0 <= 7'b001_0010;//5		
		4'd6: 	 led0 <= 7'b000_0010;//6									
		4'd7: 	 led0 <= 7'b111_1000;//7			
		4'd8:	 led0 <= 7'b000_0000;//8 			
		4'd9: 	 led0 <= 7'b001_0000;//9				
		default: led0 <= 7'b111_1111;					
	endcase
end


//10s数码管
always@(cnt1)
begin
	case (cnt1)
		4'd0:	 led1 <= 7'b100_0000;//0 
		4'd1:	 led1 <= 7'b111_1001;//1 		
		4'd2: 	 led1 <= 7'b010_0100;//2								
		4'd3: 	 led1 <= 7'b011_0000;//3		
		4'd4: 	 led1 <= 7'b001_1001;//4								
		4'd5: 	 led1 <= 7'b001_0010;//5
		default: led1 <= 7'b111_1111;
	endcase
end


//1min数码管
always@(cnt2)
begin
	case (cnt2)
		4'd0:	 led2 <= 7'b100_0000;//0 
		4'd1:	 led2 <= 7'b111_1001;//1 		
		4'd2: 	 led2 <= 7'b010_0100;//2								
		4'd3: 	 led2 <= 7'b011_0000;//3		
		4'd4: 	 led2 <= 7'b001_1001;//4								
		4'd5: 	 led2 <= 7'b001_0010;//5		
		4'd6: 	 led2 <= 7'b000_0010;//6									
		4'd7: 	 led2 <= 7'b111_1000;//7			
		4'd8:	 led2 <= 7'b000_0000;//8 			
		4'd9: 	 led2 <= 7'b001_0000;//9				
		default: led2 <= 7'b111_1111;	
	endcase
end

	
//10min数码管
always@(cnt3)
begin
	case (cnt3)
		4'd0:	 led3 <= 7'b100_0000;//0 
		4'd1:	 led3 <= 7'b111_1001;//1 		
		4'd2: 	 led3 <= 7'b010_0100;//2								
		4'd3: 	 led3 <= 7'b011_0000;//3		
		4'd4: 	 led3 <= 7'b001_1001;//4								
		4'd5: 	 led3 <= 7'b001_0010;//5
		default: led3 <= 7'b111_1111;
    endcase
end


//1h数码管	
always@(cnt4)
begin
    case (cnt4)
		4'd0:	 led4 <= 7'b100_0000;//0 
		4'd1:	 led4 <= 7'b111_1001;//1 		
		4'd2: 	 led4 <= 7'b010_0100;//2								
		4'd3: 	 led4 <= 7'b011_0000;//3		
		4'd4: 	 led4 <= 7'b001_1001;//4								
		4'd5: 	 led4 <= 7'b001_0010;//5		
		4'd6: 	 led4 <= 7'b000_0010;//6									
		4'd7: 	 led4 <= 7'b111_1000;//7			
		4'd8:	 led4 <= 7'b000_0000;//8 			
		4'd9: 	 led4 <= 7'b001_0000;//9				
		default: led4 <= 7'b111_1111;	
    endcase
end

	
//10h数码管
always@(cnt5)
begin
    case (cnt5)
		4'd0:	 led5 <= 7'b100_0000;//0 
		4'd1:	 led5 <= 7'b111_1001;//1 		
		4'd2: 	 led5 <= 7'b010_0100;//2
        default: led5 <= 7'b111_1111;
    endcase
end

endmodule