shift register

1.4 bits shift register

module top_module(
    input clk,
    input areset,  // async active-high reset to zero
    input load,
    input ena,
    input [3:0] data,
    output reg [3:0] q); 
    
    
    always @(posedge clk or posedge areset)begin
        if(areset)
            q <= 4'b0;
        else if(load)
            q [3:0]<= data [3:0];
        else if(ena) begin
            q [2:0] <= q[3:1];
            q [3] <= 1'b0;
            
        end     
    end
endmodule

要注意if的用法，在hdlbits中if语句中可执行的好像只能是一行，我会在接下来的实验中继续试验。

rotate 100

module top_module(
	input clk,
	input load,
	input [1:0] ena,
	input [99:0] data,
	output reg [99:0] q);
	
	// This rotator has 4 modes:
	//   load
	//   rotate left
	//   rotate right
	//   do nothing
	// I used vector part-select and concatenation to express a rotation.
	// Edge-sensitive always block: Use non-blocking assignments.
	always @(posedge clk) begin
		if (load)		// Load
			q <= data;
		else if (ena == 2'h1)	// Rotate right
			q <= {q[0], q[99:1]};
		else if (ena == 2'h2)	// Rotate left
			q <= {q[98:0], q[99]};
	end
endmodule

从我的角度上来讲，一开始我多加了一个寄存器用来进行交换，后来寄存器之间相互交换也需要延迟，这就是我出错误的结果，不知道在实际的中能否直接进行赋值？

shift18:考的就是逻辑移位和算术移位

module top_module(
    input clk,
    input load,
    input ena,
    input [1:0] amount,
    input [63:0] data,
    output reg [63:0] q); 
    
    always @(posedge clk)begin
        if(load)
            q <= data;
        else if(ena)begin
            if(amount == 2'b00)
                q [63:0] <= {q[62:0],1'b0};
            else if(amount == 2'b01)
                q [63:0] <= {q[55:0],8'b0};
            else if(amount == 2'b10)
                q [63:0] <= {q[63],q[63:1]};
            else if(amount == 2'b11)
                q [63:0] <= {{8{q[63]}},q[63:8]};
            
        end
        else
            q <= q;
    end

endmodule

lsfr5

module top_module(
	input clk,
	input reset,
	output reg [4:0] q);
	
	reg [4:0] q_next;		// q_next is not a register

	// Convenience: Create a combinational block of logic that computes
	// what the next value should be. For shorter code, I first shift
	// all of the values and then override the two bit positions that have taps.
	// A logic synthesizer creates a circuit that behaves as if the code were
	// executed sequentially, so later assignments override earlier ones.
	// Combinational always block: Use blocking assignments.
	always @(*) begin
		q_next = q[4:1];	// Shift all the bits. This is incorrect for q_next[4] and q_next[2]
		q_next[4] = q[0];	// Give q_next[4] and q_next[2] their correct assignments
		q_next[2] = q[3] ^ q[0];
	end
	
	
	// This is just a set of DFFs. I chose to compute the connections between the
	// DFFs above in its own combinational always block, but you can combine them if you wish.
	// You'll get the same circuit either way.
	// Edge-triggered always block: Use non-blocking assignments.
	always @(posedge clk) begin
		if (reset)
			q <= 5'h1;
		else
			q <= q_next;
	end
	
endmodule

好好看好好学。