module top(
input sys_clk_50m,
input sys_rst_n,
output [2:0] vga_r,
output [2:0] vga_g,
output [1:0] vga_b,
output vga_hsy,
output vga_vsy
);
vga_countroller uut_vga_countroller (
.clk(sys_clk_50m),
.rst(sys_rst_n),
.vga_r(vga_r),
.vga_g(vga_g),
.vga_b(vga_b),
.vga_hsy(vga_hsy),
.vga_vsy(vga_vsy)
);
endmodule
module vga_countroller(
input clk,
input rst,
output [2:0] vga_r,
output [2:0] vga_g,
output [1:0] vga_b,
output reg vga_hsy,
output reg vga_vsy
);
//VGA_Timeing 800*600 & 50MHZ & 72MHZ
parameter VGA_HTT = 12'd1040-12'd1;//Hor Total Time 行帧长
parameter VGA_HST = 12'd120; //Hor Sync Time 同步脉冲
parameter VGA_HBP = 12'd64; //Hor Back Porch 后沿脉冲
parameter VGA_HVT = 12'd800; //Hor Valid Time 显示脉冲
parameter VGA_HFP = 12'd56; //Hor Fron