Exams/2013 q2bfsm

module top_module (
    input clk,
    input resetn,    // active-low synchronous reset
    input x,
    input y,
    output f,
    output g
); 
    parameter S0=0,S1=1,S2=2,S3=3,S4=4,S5=5,S6=6,S7=7,S8=8;
    reg [3:0] state,next_state;
    reg pre_resetn;
    always@(posedge clk) begin
        if(~resetn)
            state<=S0;
        else
            state<=next_state;
    end
	
    always@(*)begin
        case(state) 
            S0: next_state = S8;
            S8: next_state = S1;
            S1: next_state = x?S2:S1; 
            S2: next_state = x?S2:S3; //x 1
            S3: next_state = x?S5:S1; //x 10
            S5: next_state = y?S7:S6;//判断第一个时钟有无1
            S6: next_state = y?S7:S4;//判断第二个时钟有无1
            S7: next_state = S7;//y永久为1
            S4: next_state = S4;//y永久为0
        endcase
    end
    always@(posedge clk) begin
        pre_resetn<=resetn;
        if(pre_resetn==0 && resetn)
        	f<=1;
        else
            f<=0;
    end
  
    //assign f=(state==S8);
    assign g=(state==S5 ||  state==S6 || state==S7);
endmodule