VL4 移位运算与乘法

//VL4
`timescale 1ns/1ns
module multi_sel(
input [7:0]d ,
input clk,
input rst,
output reg input_grant,
output reg [10:0]out
);
//*************code***********//
   reg [1:0] counter;
   reg [7:0] d_r;
   
   always@(posedge clk or negedge rst) begin
	if(!rst) 
		counter <= 0;
	else if(counter == 3)
		counter <= 0;
	else 
		counter <= counter + 1;
   end
   
   always@(posedge clk or negedge rst) begin
	if(!rst) begin
		input_grant <= 0;
		out <= 0;
		d_r <= 0;
	end 
	else begin
		case(counter)
			0: begin input_grant <= 1; d_r <= d;   out <= d; end
			1: begin input_grant <= 0; d_r <= d_r; out <= d_r*3; end
			2: begin input_grant <= 0; d_r <= d_r; out <= d_r*7; end
			3: begin input_grant <= 0; d_r <= d_r; out <= d_r*8; end
		endcase
	end
   end

//*************code***********//
endmodule

`timescale 1ns/1ns
module testbench();
	reg clk=1;
	always #5 clk = ~clk;  // Create clock with period=10
	reg rst;
// A testbench
    reg [7:0] d;
    wire input_grant;
    wire [10:0] out;

    multi_sel dut(.clk(clk),
              .rst(rst),
              .d(d),
              .input_grant(input_grant),
              .out(out));
    
    initial begin
	rst = 1'b0; d = 8'd143;
	#10 rst = 1'b1;
	#30 d = 8'd7;
	#50 d = 8'd6;
	#10 d = 8'd128;
	#10 d = 8'd129;
    #60 $finish();
	end
    
    
//end    
  initial begin
    $dumpfile("out.vcd");
    // This will dump all signal, which may not be useful
    //$dumpvars;
    // dumping only this module
    //$dumpvars(1, testbench);
    // dumping only these variable
    // the first number (level) is actually useless
    $dumpvars(0, testbench);
end  
    
endmodule