奇数分频

1.需要两个计数器，时钟上升沿计数count_p和时钟下降沿count_n计数，相差半个T。

2.计数N个状态，0-（N-1），if（count == (N-1)） count <= ‘d0;

3.计数0-(N>>1)周期为高电平，((N>>1)+1)- (N-1)为低电平，占空比大于50%，后续clk_p与clk_n使用与逻辑。

//-------------------------------------与逻辑----------------------------------
module divfrequ
#( parameter N = 5 )
( 
    input clk,
    input rst_n,
    output clk_divider
);

reg [N>>1:0]    count_p;
reg [N>>1:0]    count_n;

reg             clk_p;
reg             clk_n;



always@(posedge clk or negedge rst_n) begin 
    if(!rst_n)
         count_p <= 'd0;
    else if(count_p == N-1)
         count_p <= 'd0;
    else  
         count_p <= count_p + 1'b1;
end 

always@(posedge clk or negedge rst_n) begin 
    if(!rst_n) 
      clk_p <= 1'b1;
	else if(count_p == (N>>1)) 
		clk_p <= 1'b0;
	else if(count_p == (N-1))
		clk_p <= 1'b1;
end 

//下降沿计数
always@(negedge clk or negedge rst_n)begin
    if(!rst_n)
       count_n <= 'd0;
    else if(count_n == N-1)
       count_n <= 'd0;
    else  
       count_n <= count_n + 1'b1;
end 

//下降沿分频 
always@(negedge clk or negedge rst_n) begin 
    if(!rst_n) 
      clk_n <= 1'b1;
	else if(count_n == (N>>1)) 
		clk_n <= 1'b0;
	else if(count_n == (N-1))
		clk_n <= 1'b1;
end 

assign clk_divider = clk_n & clk_p;
endmodule 

 

 

1. 需要两个计数器，时钟上升沿计数count_p和时钟下降沿count_n计数，相差半个T。
2. 计数N个状态，0-（N-1），if（count == (N-1)） count <= ‘d0;
3. 计数0-(N>>1)周期为低电平，((N>>1)+1)- (N-1)为低电平，占空比小于50%，后续clk_p与clk_n使用或逻辑。

module divfrequ
#( parameter N = 5)
(
	input 		clk,
	input 		rst_n,
	output 		clk_divider
);
	reg [N>>1:0] 	count_p;
    reg [N>>1:0] 	count_n;
	reg				clk_p;
    reg             clk_n;
	
	//count_p
	always@(posedge clk or negedge rst_n) begin
		if(!rst_n) 
			count_p <= 'd0;
		else if(count_p == (N-1))
			count_p <= 'd0;
		else 
			count_p <= count_p + 1'b1;
	end
	
	//clk_p
	always@(posedge clk or negedge rst_n) begin
		if(!rst_n)
			clk_p <= 1'b0;
		else if(count_p == (N-1))
			clk_p <= 1'b0;
		else if(count_p == (N>>1))
			clk_p <= 1'b1;
	end
	
	//count_n
	always@(negedge clk or negedge rst_n) begin
		if(!rst_n) 
			count_n <= 'd0;
		else if(count_n == (N-1))
			count_n <= 'd0;
		else 
			count_n <= count_n + 1'b1;
	end
	
	//clk_n
	always@(negedge clk or negedge rst_n) begin
		if(!rst_n)
			clk_n <= 1'b0;
		else if(count_n == (N-1))
			clk_n <= 1'b0;
		else if(count_n == (N>>1))
			clk_n <= 1'b1;
	end
	
	assign clk_divider = clk_p | clk_n;
	
endmodule

 

 

`timescale 1ns/1ns
module divfrequ_tb();
	reg 			clk;
	reg 			rst_n;
	wire			clk_divider;

	parameter div_num = 5;
	
	initial begin
		clk = 1'b0;
		forever 
			#10 clk = ~clk;
	end

	initial begin
		rst_n = 1'b0;
		#30 rst_n = 1'b1; 
	end


	divfrequ 
	#(div_num) u_divfrequ
	( 
		clk,
		rst_n,
		clk_divider
	);


endmodule