module compare(a,b,equal);
input wire a;
input wire b;
output reg equal;
always@(a or b)//a,b任一发生变化运行下面代码:
if(a==b)
equal = 1;
else
equal = 0;
endmodule
FPGA实现简单的比较器
最新推荐文章于 2024-08-24 04:44:41 发布
module compare(a,b,equal);
input wire a;
input wire b;
output reg equal;
always@(a or b)//a,b任一发生变化运行下面代码:
if(a==b)
equal = 1;
else
equal = 0;
endmodule