| 10-4线优先级编码器 module encoder_0( input [8:0] IN9 , output reg [3:0] OUT4 ); always@(IN) begin if(IN[8]) OUT = 4’b0110; else if(IN[7]) OUT = 4’b0111; else if(IN[6]) OUT = 4’b1000; else if(IN[5]) OUT = 4’b1001; else if(IN[4]) OUT = 4’b1010; else if(IN[3]) OUT = 4’b1011; else if(IN[2]) OUT = 4’b1100; else if(IN[1]) OUT = 4’b1101; else if(IN[0]) OUT = 4’b1110; else OUT = 4’b1111 end endmodule module key_encoder( input [9:0] S_n , output wire[3:0] L , output wire GS ); wire [3:0] L_temp;
encoder_0 encoder (S_n[9:1], L_temp);
assign GS = ~((&(~L)) & S_n[0]);
assign L = ~L_temp;
endmodule 时序乘法逻辑 module multi_sel( input [7:0]d , input clk, input rst, output reg input_grant, output reg [10:0]out ); reg [1:0]cnt; reg [7:0]din; always@(posedge clk or negedge rst) begin if(!rst) begin cnt <= 0; out <= 0; input_grant <= 0; din <= 0; end else begin cnt <= cnt+1; case (cnt) 0: begin din <= d; input_grant <= 1; out <= d; end 1: begin input_grant <= 0; out <= (din<<2)-din; end 2: begin input_grant <= 0; out <= (din<<3)-din; end 3: begin input_grant <= 0; out <= (din<<3); end endcase end end endmodule BCD码计数器 module bcd_24(clk, rst_n, en, dout);
input clk, rst_n, en; output[7:0] dout; reg[7:0] dout;
always@(posedge clk or negedge rst_n) begin if(!rst_n) dout <= 8'b00000000; else if(en == 1'b0) dout <= dout; else if( (dout[7:4] == 4'b0010)&&(dout[3:0] == 4'b0011) ) dout <= 8'b00000000; else if(dout[3:0] == 4'b1001) begin dout[3:0] <= 4'b0000; dout[7:4] <= dout[7:4] + 1'b1; end else begin dout[7:4] <= dout[7:4]; dout[3:0] <= dout[3:0] + 1'b1; end end endmodule |
07-04
1万+
1万+
10-11
5781
5781
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