真值表:
输入 | 输出 | ||||
X3 | X2 | X1 | X0 | Y1 | Y0 |
0 | 0 | 0 | 1 | 0 | 0 |
0 | 0 | 1 | X | 0 | 1 |
0 | 1 | X | X | 1 | 0 |
1 | X | X | X | 1 | 1 |
VHDLH实现:
library ieee;
use ieee.std_logic_1164.all;
entity encode 4_2 is
port(input:in std_logic_vector(3 downtown 0);
output:out std_logic_vector(1 downto 0));
end encode 4_2;
architecture encode 4_2_behavior of encode 4_2 is
begin
process(input)
begin
if input(3)='1' then
output<=“11”;
elsif input(2)='1' then
output<=“10”;
elsif input(1)='1' then
output<=“01”;
elsif input(0)='1' then
output<=“00”;
else
null;
end if;
end process;
end encode 4_2_behavior;
注意:该编码器没有使能端,后文中加上了使能端。