HDLBits-Verilog:Countslow

Build a decade counter that counts from 0 through 9, inclusive, with a period of 10. The reset input is synchronous, and should reset the counter to 0. We want to be able to pause the counter rather than always incrementing every clock cycle, so the slowena input indicates when the counter should increment.

module top_module (
    input clk,
    input slowena,
    input reset,
    output [3:0] q);
​
    always@(posedge clk) begin
        if(reset)begin
            q<=0;
        end
        else if(!slowena)begin
            q<=q;
        end
        else if(q>=4'd9) begin//注意这里不可以是<9,那全是0了；也不可是>9，那样达到10了才归零
            q<=0;
        end
        else begin
            q<=q+1'b1;
        end
    end
    
endmodule