在用Modelsim仿真NCO IP核的时候报出了如下错误
# ** Error: (vsim-3033) D:/CODE/nco/prj/ip/nco_st.v(116): Instantiation of 'asj_nco_fxx' failed. The design unit was not found.
#
# Region: /nco_tb/i_nco/nco_st_inst
# Searched libraries:
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/220model
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/sgate
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera_mf
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera_lnsim
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/cycloneive
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# ** Error: (vsim-3033) D:/CODE/nco/prj/ip/nco_st.v(129): Instantiation of 'asj_altqmcpipe' failed. The design unit was not found.
#
# Region: /nco_tb/i_nco/nco_st_inst
# Searched libraries:
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/220model
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/sgate
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera_mf
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera_lnsim
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/cycloneive
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# ** Error: (vsim-3033) D:/CODE/nco/prj/ip/nco_st.v(147): Instantiation of 'asj_dxx_g' failed. The design unit was not found.
#
# Region: /nco_tb/i_nco/nco_st_inst
# Searched libraries:
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/220model
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/sgate
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera_mf
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera_lnsim
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/cycloneive
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# ** Error: (vsim-3033) D:/CODE/nco/prj/ip/nco_st.v(156): Instantiation of 'asj_dxx' failed. The design unit was not found.
#
# Region: /nco_tb/i_nco/nco_st_inst
# Searched libraries:
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/220model
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/sgate
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera_mf
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera_lnsim
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/cycloneive
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# ** Error: (vsim-3033) D:/CODE/nco/prj/ip/nco_st.v(163): Instantiation of 'asj_nco_apr_dxx' failed. The design unit was not found.
#
# Region: /nco_tb/i_nco/nco_st_inst
# Searched libraries:
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/220model
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/sgate
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera_mf
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera_lnsim
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/cycloneive
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# ** Error: (vsim-3033) D:/CODE/nco/prj/ip/nco_st.v(178): Instantiation of 'asj_nco_pxx' failed. The design unit was not found.
#
# Region: /nco_tb/i_nco/nco_st_inst
# Searched libraries:
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/220model
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/sgate
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera_mf
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera_lnsim
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/cycloneive
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# ** Error: (vsim-3033) D:/CODE/nco/prj/ip/nco_st.v(191): Instantiation of 'asj_gam_dp' failed. The design unit was not found.
#
# Region: /nco_tb/i_nco/nco_st_inst
# Searched libraries:
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/220model
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/sgate
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera_mf
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera_lnsim
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/cycloneive
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# ** Error: (vsim-3033) D:/CODE/nco/prj/ip/nco_st.v(203): Instantiation of 'asj_nco_as_m_dp_cen' failed. The design unit was not found.
#
# Region: /nco_tb/i_nco/nco_st_inst
# Searched libraries:
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/220model
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/sgate
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera_mf
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera_lnsim
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/cycloneive
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# ** Error: (vsim-3033) D:/CODE/nco/prj/ip/nco_st.v(215): Instantiation of 'asj_nco_as_m_cen' failed. The design unit was not found.
#
# Region: /nco_tb/i_nco/nco_st_inst
# Searched libraries:
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/220model
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/sgate
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera_mf
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera_lnsim
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/cycloneive
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# ** Error: (vsim-3033) D:/CODE/nco/prj/ip/nco_st.v(227): Instantiation of 'asj_nco_as_m_cen' failed. The design unit was not found.
#
# Region: /nco_tb/i_nco/nco_st_inst
# Searched libraries:
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/220model
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/sgate
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera_mf
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera_lnsim
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/cycloneive
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# ** Error: (vsim-3033) D:/CODE/nco/prj/ip/nco_st.v(241): Instantiation of 'asj_nco_madx_cen' failed. The design unit was not found.
#
# Region: /nco_tb/i_nco/nco_st_inst
# Searched libraries:
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/220model
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/sgate
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera_mf
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera_lnsim
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/cycloneive
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# ** Error: (vsim-3033) D:/CODE/nco/prj/ip/nco_st.v(252): Instantiation of 'asj_nco_mady_cen' failed. The design unit was not found.
#
# Region: /nco_tb/i_nco/nco_st_inst
# Searched libraries:
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/220model
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/sgate
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera_mf
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera_lnsim
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/cycloneive
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# ** Error: (vsim-3033) D:/CODE/nco/prj/ip/nco_st.v(265): Instantiation of 'asj_nco_derot' failed. The design unit was not found.
#
# Region: /nco_tb/i_nco/nco_st_inst
# Searched libraries:
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/220model
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/sgate
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera_mf
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera_lnsim
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/cycloneive
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# ** Error: (vsim-3033) D:/CODE/nco/prj/ip/nco_st.v(274): Instantiation of 'asj_nco_mob_w' failed. The design unit was not found.
#
# Region: /nco_tb/i_nco/nco_st_inst
# Searched libraries:
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/220model
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/sgate
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera_mf
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera_lnsim
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/cycloneive
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# ** Error: (vsim-3033) D:/CODE/nco/prj/ip/nco_st.v(283): Instantiation of 'asj_nco_mob_w' failed. The design unit was not found.
#
# Region: /nco_tb/i_nco/nco_st_inst
# Searched libraries:
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/220model
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/sgate
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera_mf
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera_lnsim
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/cycloneive
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# ** Error: (vsim-3033) D:/CODE/nco/prj/ip/nco_st.v(295): Instantiation of 'asj_nco_isdr' failed. The design unit was not found.
#
# Region: /nco_tb/i_nco/nco_st_inst
# Searched libraries:
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/220model
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/sgate
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera_mf
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/altera_lnsim
# D:/intelFPGA/13.0/modelsim_ase/altera/verilog/cycloneive
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
# D:/CODE/nco/prj/simulation/modelsim/rtl_work
解决方法:
-
找到asj库文件的存放文件夹 D:/CODE/nco/prj/ip/nco-library/
-
然后把这个文件夹添加到 Simulate—>Start Simulation…—>Libraries里面
-
然后在Modelsim中重新对nco.vo和nco_tb.v文件进行编译 Compile—>Compile…
-
然后在Modelsim中重新进行仿真 Simulate—>Start Simulation…
-
然后就会出现这个界面
-
然后弹出波形窗口以后依次点击①Restart 和 ②Run -All就会开始出现波形
最后注意,由于NCO IP核仿真需要占用较大的磁盘空间,因此如果磁盘比较小的话可能会出现因为磁盘被占满而仿真中断的情况。
所以遇到仿真中断的情况的时候需要返回去看一下是否磁盘被占满了。