[HDLBits] Tb/tb2

The waveform below sets clk, in, and s:

051015202530354045505560657075clkins26270

Module q7 has the following declaration:

module q7 (
    input clk,
    input in,
    input [2:0] s,
    output out
);

Write a testbench that instantiates module q7 and generates these input signals exactly as shown in the waveform above.

`timescale 1ps/1ps
module top_module();
	reg clk,in,out;
    reg [2:0]s;
    parameter period=10;
    q7 q_u(
        .clk  (clk),
        .in	  (in),
        .s    (s),
        .out  (out)
    );
    always #(period/2) clk=~clk;
    initial begin
        clk=0;
        in=0;
        s=2;
        #10 s=6;
        #10 s=2;
        	in=1;
        #10 s=7;
        	in=0;
        #10 s=0;
        	in=1;
        #30 in=0;
    end
endmodule