Verilog刷题HDLBits——Tb/tb2

题目描述

The waveform below sets clk, in, and s:

Module q7 has the following declaration:

module q7 (
    input clk,
    input in,
    input [2:0] s,
    output out
);

Write a testbench that instantiates module q7 and generates these input signals exactly as shown in the waveform above.

代码

module top_module();
    parameter clk_period=10;
    reg clk;
    initial clk=0;
    always #(clk_period/2) clk=~clk;
    wire out;
    reg in;
    reg[2:0] s;
    initial
        begin
            in=0;
            s=2;
            #10 s=6;
            #10 in=1;
            	s=2;
            #10 in=0;
            	s=7;
            #10 in=1;
            	s=0;
            #30 in=0;
        end
    
    q7 inst_q7(clk,in,s,out);

endmodule

结果