Tb/tb2_HDLbits(简单的testbench)

 Module q7 has the following declaration:

module q7 (
    input clk,
    input in,
    input [2:0] s,
    output out
);

Write a testbench that instantiates module q7 and generates these input signals exactly as shown in the waveform above.

`timescale 1ps/1ps
module top_module();
	reg clk,in;
    reg[2:0]s;
    wire out;
    
    always begin  #5 clk=~clk;
        end
    
    initial begin
        clk=0;
        in=0;
        s=2;
        #10 s=6;
        #10 s=2;  in=1;
        #10 s=7;  in=0;
        #10 s=0; in=1;
        #30 in=0;
    end
    q7 i1( clk,  in, s, out);
    
endmodule