ad_lvds_clk 将外部时钟同步到本芯片的时钟网络代码

module ad_lvds_clk (

  clk_in_p,
  clk_in_n,
  clk);

  parameter   DEVICE_TYPE       = 0;
  localparam  SERIES7       = 0;
  localparam  VIRTEX6       = 1;

  input     clk_in_p;
  input     clk_in_n;
  output    clk;

  // wires

  wire      clk_ibuf_s;

  // instantiations

  IBUFGDS i_rx_clk_ibuf (
    .I (clk_in_p),
    .IB (clk_in_n),
    .O (clk_ibuf_s));

  generate
  if (DEVICE_TYPE == VIRTEX6) begin
  BUFR #(.BUFR_DIVIDE("BYPASS")) i_clk_rbuf (
    .CLR (1'b0),
    .CE (1'b1),
    .I (clk_ibuf_s),
    .O (clk));
  end else begin
  BUFG i_clk_gbuf (
    .I (clk_ibuf_s),
    .O (clk));
  end
  endgenerate



endmodule