verilog-mode的简要介绍

verilog-mode是什么
官网的介绍（https://www.veripool.org/wiki/verilog-mode）:
Verilog-mode.el is the extremely popular free Verilog mode for Emacs which provides context-sensitive highlighting, auto indenting, and provides macro expansion capabilities to greatly reduce Verilog coding time. It supports AUTOs and indentation in Emacs for traditional Verilog (1394-2005), the Open Verification Methodology (OVM) and SystemVerilog (1800-2005/1800-2009).
Recent versions allow you to insert AUTOS in non-AUTO designs, so IP interconnect can be easily modified. You can also expand SystemVerilog “.*” port instantiations, to see what ports will be connected by the simulators.
简单点说就是支持Verilog、SystemVerilog（包括UVM）的emacs语法高亮文件。其中提到Verilog-mode支持Autos——这就是今天的重点。

Verilog-mode是由Michael McNamara mac@verilog.com和Wilson Snyder wsnyder@wsnyder.org编写。难能可贵的是，这个verilog-mode保持着每月都有更新。

值得一提的是Wilson Snyder就是SystemVerilog开源仿真器Verilator的作者。
verilog-mode Autos有哪些功能
手动编写的verilog代码：

module example (/*AUTOARG*/);
  input i;
  output o;
  /*AUTOINPUT*/
  /*AUTOOUTPUT*/
  /*AUTOREG*/

  inst inst (/*AUTOINST*/);

  always @ (/*AUTOSENSE*/) begin
    o = i;
  end

endmodule

由Autos处理后的Verilog代码：

module example (/*AUTOARG*/
  // Outputs
  lower_out, o,
  // Inputs
  lower_inb, lower_ina, i
  );
  input i;
  output o;
  /*AUTOINPUT*/
  // Beginning of automatic inputs
  input  lower_ina; // To inst of inst.v
  input  lower_inb; // To inst of inst.v
  // End of automatics
  /*AUTOOUTPUT*/
  // Beginning of automatic output
  output lower_out; // From inst of inst.v
  // End of automactics
  /*AUTOREG*/
  // Beginning of automatic regs
  reg    o;
  // End of automatics

  inst inst (/*AUTOINST*
             // Outputs
             .lower_out (lower_out),
             // Inputs
             .lower_inb (lower_inb),
             .lower_ina (lower_ina));

  always @ (/*AUTOSENSE*/i) begin
    o = i;
  end

大家可以看到，verilog-mode自动分析出：
模块的端口输入和输出
内部变量
敏感信号列表
提取子模块的端口定义
自动提取子模块的端口定义来连线是今天的重点中的重点。一般来讲，我们实例化模块时大部分的信号名与子模块定义的名字一致即可。如上面代码中的：

  inst inst (/*AUTOINST*
             // Outputs
             .lower_out (lower_out),
             // Inputs
             .lower_inb (lower_inb),
             .lower_ina (lower_ina));

特殊连接关系的处理
但常常我们顶层连接时会换一个名字。比如module A有一个输出端口dat_o，module B有一个输入端口dat_i，这两者怎么连？定义模版AUTO_TEMPLATE，如下：
手动编写的verilog：

/* A AUTO_TMEPLATE (
  .dat_o (dat_a2b),
)
*/
A u_A (/*AUTOINST*/);

/* B AUTO_TEMPLATE (
  .dat_i (dat_a2b),
)
*/
B u_B (/*AUTOINST*/);

由Autos处理后的verilog代码：

/* A AUTO_TMEPLATE (
  .dat_o (dat_a2b),
)
*/
A u_A (/*AUTOINST*/
       // Outputs
       .dat_o  (dat_a2b));  // Templated

/* B AUTO_TEMPLATE (
  .dat_i (dat_a2b),
)
*/
B u_B (/*AUTOINST*/
       // Inputs
       .dat_i  (dat_a2b));  // Templated

在哪里找子模块定义？
默认规则：
当前文件夹下找
当前找不到怎么办，指定搜索路径（与verilog仿真器的参数-y一样）
使用方法：在顶层endmodule后面指定verilog-library-directories，如下：

endmodule // top

// Local Variables:
// verilog-library-directories:("." "subdir" "subdirs")
// End:

除了写模版还需要做什么？
只需要Ctrl-C Ctrl-A，仅此而已。
如果修改了子模块或者模版，再按一次Ctrl-C Ctrl-A。
更多功能

    verilog-auto-arg          for AUTOARG module instantiations
    verilog-auto-ascii-enum   for AUTOASCIIENUM enumeration decoding
    verilog-auto-assign-modport for AUTOASSIGNMODPORT assignment to/from modport
    verilog-auto-inout        for AUTOINOUT making hierarchy inouts
    verilog-auto-inout-comp   for AUTOINOUTCOMP copy complemented i/o
    verilog-auto-inout-in     for AUTOINOUTIN inputs for all i/o
    verilog-auto-inout-modport  for AUTOINOUTMODPORT i/o from an interface modport
    verilog-auto-inout-module for AUTOINOUTMODULE copying i/o from elsewhere
    verilog-auto-inout-param  for AUTOINOUTPARAM copying params from elsewhere
    verilog-auto-input        for AUTOINPUT making hierarchy inputs
    verilog-auto-insert-lisp  for AUTOINSERTLISP insert code from lisp function
    verilog-auto-insert-last  for AUTOINSERTLAST insert code from lisp function
    verilog-auto-inst         for AUTOINST instantiation pins
    verilog-auto-star         for AUTOINST .* SystemVerilog pins
    verilog-auto-inst-param   for AUTOINSTPARAM instantiation params
    verilog-auto-logic        for AUTOLOGIC declaring logic signals
    verilog-auto-output       for AUTOOUTPUT making hierarchy outputs
    verilog-auto-output-every for AUTOOUTPUTEVERY making all outputs
    verilog-auto-reg          for AUTOREG registers
    verilog-auto-reg-input    for AUTOREGINPUT instantiation registers
    verilog-auto-reset        for AUTORESET flop resets
    verilog-auto-sense        for AUTOSENSE or AS always sensitivity lists
    verilog-auto-tieoff       for AUTOTIEOFF output tieoffs
    verilog-auto-undef        for AUTOUNDEF \=`undef of local \=`defines
    verilog-auto-unused       for AUTOUNUSED unused inputs/inouts
    verilog-auto-wire         for AUTOWIRE instantiation wires

    verilog-read-defines      for reading \=`define values
    verilog-read-includes     for reading \=`includes

详见官网帮助文档：
https://www.veripool.org/projects/verilog-mode/wiki/Verilog-mode-Help

verilog-mode下载、安装
新版的GNU Emacs自带verilog-mode，如果需要最新的verilog-mode可以在官网下载：
https://www.veripool.org/projects/verilog-mode/wiki/Installing

VIM用户咋办？
可以用VIM调动shell命令执行（emacs批处理模式），例如：
:!emacs --batch <filenames.v> -f verilog-batch-auto