前言
This is the source distribution repository for verilog-mode, the Verilog editing and AUTOs package which is part of GNU Emacs (lisp/progmodes/verilog-mode.el).
Verilog-Mode supports syntax highlighting of SystemVerilog (IEEE 1800-2017), Verilog (IEEE 1364-2005), and the Universal Verification Modeling language (UVM). Verilog-Mode also has AUTOs which greatly accelerate maintaining interconnect, resets, and other boiler-plate code.
首先必须特别感谢大佬GXX的各种支持,终于安装成功!然后开始正文~
简而言之,我们通常使用的verilog-mode是基于emacs的,适配于vim的verilog语法适配以及自动声明、例化、连线工具。
全球最大同性交友网站github导航:
GitHub - veripool/verilog-mode: Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs