- 博客(3)
- 资源 (8)
- 收藏
- 关注
原创 Timing相关
1、minimum pulse width summaryReports the results of minimum pulse width and minimum period checks.A minimum pulse width check verifies that a clock high ("High") or low("Low") pulse sustains long
2017-11-15 17:27:55 531
原创 verilog testbench编写笔记
1 . initial模块赋值时注意在时钟上升沿打入数据initialbegin ax = 16'd0; ay = 11'd0; bx = 16'd0; by = 11'd0; enb1 = 1'b0; enb2 = 1'b0; enb3 = 1'b0; accum = 1'b0; loadconst = 1'b...
2017-11-15 15:53:22 2160
IEEE 802.15.4A-2011.pdf
2020-05-30
基于verilog代码实现四线制spi接口设计及仿真工程.zip
2019-07-22
空空如也
TA创建的收藏夹 TA关注的收藏夹
TA关注的人