reg signed [4 : 0] a = -5'd3;
reg signed [3 : 0] b = -4'd4;
reg signed [4 : 0] sum;
wire signed [5 : 0] sum_temp;
//tb
initial begin
a = -5'd14;
b = -4'd4;
#100;
a = -5'd15;
b = 4'd4;
#100;
a = 5'd15;
b = 4'd4;
#100;
a = -5'd2;
b = 4'd4;
#100;
a = 5'd3;
b = 4'd4;
#100;
a = -5'd5;
b = -4'd4;
end
assign sum_temp = a + b;
always @ (posedge clka )
begin
case(sum_temp[5:4])
2'b01: sum <= 5'd15; //正溢
2'b10: sum <= -5'd16; //负溢
2'b00,2'b11: sum <= {sum_temp[5],sum_temp[3:0]}; //无溢出
default: sum <= {sum_temp[5],sum_temp[3:0]};
endcase
end