好长时间了想搞懂dc的脚本书写 终于让我找见一个好的教程 写的非常详细 弄过来给大家参考。
Design CompilerTutorial
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Before running synthesis the tool environmentfile must be sourced. If you have not done this please go back tothe environment setup page. All steps on this page may be completed from atelnet or ssh window.
1.Create a .synopsys_dc.setup environment file inyour home directory specifying the location of the technologylibrary files you want to use. Here is one premade that points toour open source technology libraries. Place a copy in your ~/ directory.
2.Write the verilog code for the part you wish to synthesize.For the purposes of this example we will use the same verilog asthe simulation tutorial:
module mux2_1 ( out, in0, in1, sel ) ;
endmodule // mux2_1
3.Next one must write a design complier script.The script. should do the following:
- Load all the verilog files into dc_shell andtell dc_shell which module is the top level module.
- Set up the constraints for compilation. Thecontraints tune how the dc_shell tool converts the behavioral RTLinto a netlist. For example one may set timing contraints or areacontraints dependent on which is more important for the design athand.
- Issue the compile command and tell dc_shell toreport back on the resultant area and timing so the designer willget feedback on the resultant design.
- Save the netlist back to a verilog format foruse in downstream tools.
Here is an example design compiler shell script. forthe mux2_1 that does all of these things:
# Load up the verilog files (when more files are includedthere
# will be more analyze lines)
analyze -format verilog ./mux2_1.v
# Tell dc_shell the name of the top level module
elaborate mux2_1
# Set timing constaints, this says that a max of .5ns of delayfrom
# input to output is alowable
set_max_delay .5 -to [all_outputs]
# Set the characteristics of the driving cell for allinputs
set_driving_cell -lib_cell INVX1 -pin Y [all_inputs]
# If this were a clocked piece of logic we could set aclock
#
# create_clock clk -period 1.800
# Check for warnings/errors
check_design
# Use module compiler for arth. DW components
set dw_prefer_mc_inside true
# ungroup everything
ungroup -flatten -all
# flatten it all, this forces all the hierarchy to be flattenedout
set_flatten true -effort high
uniquify
# This forces the compiler to spend as much effort (andtime)
# compiling this RTL to achieve timing possible.
compile_ultra
# Now that the compile is complete report on the results
report_area
report_timing
# Finally write the post synthesis netlist out to a verilogfile
write -f verilog mux2_1 -output mux2_1_post_synth.v -hierarchy
exit
4.Now everything is set to compile the mux. Do doso issue the command shown in red in the directory containing thefiles listed above.
pgratz@deskworkingdir $ dc_shell-t -f mux2_1.dc_cmd |tee output.txt
5.Assuming no errors occur there will be severalnew files in your directory once dc_shell is done. The first one tolook at is the output.txt file. This is the log of the compileoutput. Looking at this copy for comparison you should look over the warnings and errors anddetermine if there were any problems durning compile. Note: somewarnings are not indicative of a problem with your design. If thewarning appears in the sample output.txt then it can safely beignored.
6.Once satisfied that there are no errors in therun you should skim down nearly to the bottom of output.txt whereyou will find some text like the following:
report_area
Information: Updating design information... (UID-85)
****************************************
Report : area
Design : mux2_1
Version: V-2004.06-SP1
Date
****************************************
Library(s) Used:
Number ofports:
Number ofnets:
Number ofcells:
Number ofreferences:
Combinationalarea:
Noncombinationalarea:
Net Interconnectarea:
Total cellarea:
Totalarea:
1
...
design is 256 "cell units".
7.Skimming further down in output.txt you will find thefollowing output: ...
report_timing
****************************************
Report : timing
Design : mux2_1
Version: V-2004.06-SP1
Date
****************************************
Operating Conditions:typical
Wire Load Model Mode: top
1
...
pico seconds. In this case it shows that the slowest paththrough the design takes .31ns. In the mux2_1.dc_cmd file we placeda constraint on the timing that
all outputs must be asserted by at least .500 ns after theinputs change and this is shown in the "data required time". The"slack" is the difference between
the worst case path and the required time. In this case timingis met so the slack is a positive .19 ps. If timing was not metthen the slack would be a
negative value.
8.Another file created during the synthesis step aboveis the "mux2_1_post_synth.v"file.
module mux2_1 ( out, in0, in1, sel );
endmodule
-
As you can see this is thepost synthesis netlist written out durning the final step in themux2_1.dc_cmd. In it the behavioral "assign" statment has beenreplaced with multiple instatiations of single bit library MUX2X1mux cells and some INVX2 inverter cells.
This completes the design compiler tutorial. Moreinformation on design compiler may be found on the main cad pageunder synthesis documentation.
Modified by Paul Gratz, pgratz@cs.utexas.edu
.synopsys_dc.setup
set search_path [list ".""/projects/cad/open_source_synth_libs/osu_stdcells/lib/tsmc018/lib""/projects/cad/synopsys/synth/libraries/syn/"
"/projects/cad/synopsys/synth/mc/lib/dp/dplite/""/projects/cad/synopsys/synth/mc/lib/dp""/projects/cad/synopsys/synth/dw/sim_ver/"]
set target_library [list osu018_stdcells.db]
set synthetic_library [list dw_foundation.sldb dw01.sldbdw02.sldb dw03.sldb dw04.sldb dw05.sldb dw06.sldb dw08.sldbdw07.sldb standard.sldb]
set link_library [concat
set command_log_file "./command.log"
define_design_lib WORK -path ./work
脚本文件
# Load up the verilog files (when more files are includedthere
# will be more analyze lines)
analyze -format verilog ./mux2_1.v
# Tell dc_shell the name of the top level module
elaborate mux2_1
# Set timing constaints, this says that a max of .5ns of delayfrom
# input to output is alowable
set_max_delay .5 -to [all_outputs]
# Set the characteristics of the driving cell for allinputs
set_driving_cell -lib_cell INVX1 -pin Y [all_inputs]
# If this were a clocked piece of logic we could set aclock
#
# create_clock clk -period 1.800
# Check for warnings/errors
check_design
# Use module compiler for arth. DW components
set dw_prefer_mc_inside true
# ungroup everything
ungroup -flatten -all
# flatten it all, this forces all the hierarchy to be flattenedout
set_flatten true -effort high
uniquify
# This forces the compiler to spend as much effort (andtime)
# compiling this RTL to achieve timing possible.
compile_ultra
# Now that the compile is complete report on the results
report_area
report_timing
# Finally write the post synthesis netlist out to a verilogfile
write -f verilog mux2_1 -output mux2_1_post_synth.v -hierarchy
exit
写好以后
在在当前目录里面运行 dc_shell-t -f mux2_1.dc_cmd |tee output.txt
就可以了
结果一般如下：
This program is proprietary and confidential information ofSynopsys, Inc.
and may be used and disclosed only as authorized in a licenseagreement
controlling such use and disclosure.
Initializing...
# Load up the verilog files (when more files are includedthere
# will be more analyze lines)
analyze -format verilog ./mux2_1.v
Running PRESTO HDLC
Compiling source file ./mux2_1.v
Presto compilation completed successfully.
1
# Tell dc_shell the name of the top level module
elaborate mux2_1
Running PRESTO HDLC
Loading db file'/projects/cad/synopsys/synth/libraries/syn/gtech.db'
Loading db file'/projects/cad/synopsys/synth/libraries/syn/standard.sldb'
Loading db file'/projects/cad/synopsys/synth/libraries/syn/dw_foundation.sldb'
Loading db file'/projects/cad/synopsys/synth/libraries/syn/dw01.sldb'
Loading db file'/projects/cad/synopsys/synth/libraries/syn/dw02.sldb'
Loading db file'/projects/cad/synopsys/synth/libraries/syn/dw03.sldb'
Loading db file'/projects/cad/synopsys/synth/libraries/syn/dw04.sldb'
Loading db file'/projects/cad/synopsys/synth/libraries/syn/dw05.sldb'
Loading db file'/projects/cad/synopsys/synth/libraries/syn/dw06.sldb'
Loading db file'/projects/cad/synopsys/synth/libraries/syn/dw08.sldb'
Loading db file'/projects/cad/synopsys/synth/libraries/syn/dw07.sldb'
Loading db file'/projects/cad/open_source_synth_libs/osu_stdcells/lib/tsmc018/lib/osu018_stdcells.db'
Presto compilation completed successfully.
Current design is now 'mux2_1'
1
# Set timing constaints, this says that a max of .5ns of delayfrom
# input to output is alowable
set_max_delay .5 -to [all_outputs]
1
# Set the characteristics of the driving cell for all inputs
set_driving_cell -lib_cell INVX1 -pin Y [all_inputs]
Warning: Design rule attributes from the driving cell will be
1
# If this were a clocked piece of logic we could set a clock
#
# create_clock clk -period 1.800
# Check for warnings/errors
check_design
1
# Use module compiler for arth. DW components
set dw_prefer_mc_inside true
true
# ungroup everything
ungroup -flatten -all
Current instance is the top-level of design 'mux2_1'.
Information: Updating design information... (UID-85)
Warning: Design has no hierarchy.
0
# flatten it all, this forces all the hierarchy to be flattenedout
set_flatten true -effort high
1
uniquify
1
# This forces the compiler to spend as much effort (and time)
# compiling this RTL to achieve timing possible.
compile_ultra
Information: Data-path optimization is enabled. (DP-1)
Information: Evaluating DesignWare library utilization.(UISN-27)
============================================================================
| DesignWare Building BlockLibrary
============================================================================
| Basic DW BuildingBlocks
| Licensed DW BuildingBlocks
============================================================================
Information: There is no timing violation in design mux2_1.Delay-based auto_ungroup will not be performed. (OPT-780)
Current design is 'mux2_1'.
1
# Now that the compile is complete report on the results
report_area
Information: Updating design information... (UID-85)
****************************************
Report : area
Design : mux2_1
Version: V-2004.06-SP1
Date
****************************************
Library(s) Used:
Number ofports:
Number ofnets:
Number ofcells:
Number ofreferences:
Combinationalarea:
Noncombinationalarea:
Net Interconnectarea:
Total cellarea:
Totalarea:
1
report_timing
****************************************
Report : timing
Design : mux2_1
Version: V-2004.06-SP1
Date
****************************************
Operating Conditions:typical
Wire Load Model Mode: top
1
# Finally write the post synthesis netlist out to a verilogfile
write -f verilog mux2_1 -output mux2_1_post_synth.v-hierarchy
1
exitInformation: Defining new variable'synlib_iis_accept_all_gened_impl'. (CMD-041)
Thank you...
基本就可以了
要注意的有两点
首先要修改设置里面的目录。
其次是脚本语言的后缀要写对
这样在没有问题执行以后
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