普通加法器与加1逻辑的面积一样吗

renzao_ai

于 2022-08-25 09:49:43 发布

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分类专栏： systemverilog verilog-2001 芯片文章标签： asic

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综合

sh  mkdir -p    ./work
define_design_lib WORK -path ./work
set_host_options -max_cores 8

set search_path ./
lappend search_path xxx/ccs_db
set             synthetic_library [list dw_foundation.sldb] 
set target_library xxx_ccs.db
set link_library "* dw_foundation.sldb $target_library"

set_svf adder.svf
#analyze -work WORK -format sverilog adder256.sv
analyze -work WORK -format sverilog addone.sv
elaborate adder -work WORK -update
link

current_design adder 

compile

report_area

return

普通加法器256

module adder(
    input [255:0] addend1,
    input [255:0] addend2,
    output logic [255:0] added,
    output logic carryin
);
   assign {carryin,added} = addend1 + addend2;
endmodule

Number of ports: 1542
Number of nets: 1794
Number of cells: 259
Number of combinational cells: 258
Number of sequential cells: 0
Number of macros/black boxes: 0
Number of buf/inv: 0
Number of references: 2

Combinational area: 2274.012051
Buf/Inv area: 0.000000
Noncombinational area: 0.000000
Macro/Black Box area: 0.000000
Net Interconnect area: undefined (Wire load has zero net area)

Total cell area: 2274.012051
Total area: undefined

adder 加1

module adder(
    input [255:0] addend1,
    output [255:0] added,
    output carrier
);
   assign {carrier, added} = addend1 + 1;
endmodule

Number of ports: 1027
Number of nets: 1281
Number of cells: 258
Number of combinational cells: 257
Number of sequential cells: 0
Number of macros/black boxes: 0
Number of buf/inv: 1
Number of references: 2

Combinational area: 1553.760028
Buf/Inv area: 0.936000
Noncombinational area: 0.000000
Macro/Black Box area: 0.000000
Net Interconnect area: undefined (Wire load has zero net area)

Total cell area: 1553.760028
Total area: undefined