Verilog实现任意进制50%占空比时钟分频

程序实现：CLK_DIV_MODULE.v

module CLK_DIV_MODULE#(
parameter   CLK_DIV_NUM     =       4
)
(
    input       i_clk,
    input       i_rst,
    output      o_clk_div
    );
        
reg [$clog2(CLK_DIV_NUM) - 1 : 0]   r_cnt;         // 7 log2的7 clog2向上取整为3 位宽减一计 计数器：0-6计数
reg                                 r_clk_p;
reg                                 r_clk_n;
        
assign                              o_clk_div    =  CLK_DIV_NUM[0] == 1 ?  (r_clk_n  ||   r_clk_p) : r_clk_p;
//奇分频 ：需要或逻辑  注意不能用翻转 因为不是偶频率 会造成占空比不是50%问题
//偶分频 ：只取上升沿
always @(posedge i_clk or posedge i_rst)
if (i_rst)
    begin
        r_cnt <= 0;
    end
else if(r_cnt == CLK_DIV_NUM - 1)
    begin
        r_cnt <= 0;
    end
else
    begin
        r_cnt <= r_cnt + 1;
    end

always @(posedge i_clk or posedge i_rst)
if (i_rst)
    begin
    r_clk_p <= 0;
    end
else if(r_cnt == CLK_DIV_NUM - 1)
    r_clk_p <= 1;
else if(r_cnt == CLK_DIV_NUM / 2 - 1)
    r_clk_p <= 0;
else
    r_clk_p <= r_clk_p;

always @(negedge i_clk or posedge i_rst)
if (i_rst)
begin
        r_clk_n <= 0;
end
else if(r_cnt == 0)
    begin
        r_clk_n <= 1;
    end
else if(r_cnt == CLK_DIV_NUM / 2)
    begin
        r_clk_n <= 0;
    end
else
        r_clk_n <= r_clk_n;
endmodule

仿真代码
TB_CLK_DIV_MODULE.v

`timescale 1ns / 1ps

`define P_CLK_PERIOD 10 //100Mhz SYS_CLK
module TB_CLK_DIV_MODULE();


reg      r_clk;
reg      r_rst;
wire     w_clk_div;

CLK_DIV_MODULE CLK_DIV_MODULE_inst0
(
    .i_clk          (r_clk),
    .i_rst          (r_rst),
    .o_clk_div      (w_clk_div)
);

initial
begin
    r_rst = 1;
    #100;
    @(posedge r_clk) r_rst = 0;
end

initial
r_clk = 1;
always #(`P_CLK_PERIOD/2) r_clk = ~r_clk;

endmodule

时序图：七分频

仿真：

时序图：六分频

仿真：