UVM – Stop Hitting Your Brother Coding Guidelines

Configuration Tips

• don't config_db the individual values, group values tnto config object
• calling set()/get() 
• group a component's configuration: env and agent
• config_db 明确路径， 减少wildcard；config_db::get如果失败，打印提示
• config 跟TB 匹配

Transaction Tips

• write the do_copy(), do_compare()
• never mix the two

Sequence Tips

• no more murky m_sequencer/p_sequencer, 你可以把sqr放到config中
• avoid the traning wheels: uvm_do

More UVM Tips

• Minimize UVM objections to test level, and maybe scoreboard, avoid in sequences, drivers, ...
• construct objects with factory create(), not new(); 可以自定义macro: my_create_o/c
• always check the result from randomize(); not assert(txn.randomize())
• checker $cast() too

Systemverilog Tips

• Single value: $urandom(n)
• avoid randcase: hard to debug
• never $random()
• avoid obscure constructs from the LRM: streaming operators; wildcard compares
• watch out for X and Z: ===