FPGA编译时出现常见的错误Critical…

先说下quartus对这个的解释：

Timing requirements not met。

CAUSE:         One or more analyses are failing timing (negative slack).

ACTION:     Analyze the design in the TimeQuest Timing Analyzer to verify that the constraints are correct, or to identify paths, which require further optimization.

其他人的说法：

    Critical Warning: Timing requirements were not met. See Report window for details.

　　原因：时序要求未满足，

　   措施：双击Compilation Report-->Time Analyzer-->红色部分（如clock setup:'clk'等）-->左键单击list path,查看fmax的SLACK REPORT再根据提示解决,有可能是程序的算法问题