32位加法器覆盖率分析（完整工程）

1 adder32.v文件

仿真工具：VCS

module adder32(a_in,b_in,c_in,sum_out,c_out);
        input  [31:0]  a_in;
        input  [31:0]  b_in;
        input          c_in;        
        output [31:0]  sum_out;
        output [0:0]   c_out;
        assign {c_out,sum_out} = a_in + b_in + c_in;
endmodule

2. timescale.v

`timescale 1ns/1ns

3 adder32_tb_random.v

module adder32_tb_random;
    reg [31:0]  ain;
    reg [31:0]  bin;
    reg         cin;
	reg         adder_cin;
    wire [31:0] sumout;
    wire 		cout;

adder32 u_adder32(
	.a_in	   (ain),
	.b_in	   (bin),
	.c_in	   (cin),
	.sum_out   (sumout),
	.c_out     (cout)
);

parameter CLK_PERIOD = 20;
reg clk, reset_n;

initial begin 
	clk = 0;
	forever begin
		#(CLK_PERIOD/2) clk = ~clk;
	end
end

initial begin
	reset_n = 0;
	#100 
	reset_n = 1;
end

integer seed;
initial begin
	if(!$value$plusargs("seed=%d",seed))begin
		seed = 100;
	end else begin
		$display("Random function with the SEED=%d", seed);
	end
end

reg [32:0] adder_sum;
always @(negedge clk) begin
	if (~reset_n) begin
		ain = 0;
		bin = 0;
		cin = 0;
	end else begin
		ain = $random(seed); 
		bin = $random(seed);
		cin = $random(seed);
		{adder_cin,adder_sum} = ain + bin +cin; //expected results
		$display("%0t: adder_sum=%0d, ain=%0d, bin=%0d, cin=%0d",$time, adder_sum, ain, bin, cin);
	end
end

//watch dog 
//question: how to setup clock cycles for simualtion?
integer cycle_num;

initial begin
	if(!$value$plusargs("cycle = %d",cycle_num))begin
		cycle_num = 10;
		$display("Simulation time is %0d cycles", cycle_num);
	end else begin
		$display("Simulation time is %0d cycles", cycle_num);
	end

	repeat (cycle_num) @(posedge clk);
	# 200 $finish;
end	

// checker
always @(posedge clk) begin
	if(!reset_n) begin
		$display("%0t: %m: Resetting...", $time);
	end else begin
		if (adder_sum != {cout,sumout}) begin
			$display("ERROR: %0t : %m: adder_sum = %d, {cout,sumout} = %d", $time, adder_sum, {cout,sumout});
		end
	end
end

initial begin
	$vcdpluson;
end
endmodule

4 Makefile

SEED = $(shell date +%s)

CYCLE_NUM =200

DUT = ./timescale.v ./adder32.v

TB = ./adder32_tb_random.v

#-----------------run the simualation throught the common methods -------------------
run: compile simulate

compile:
	vcs -debug_acc+all -full64  -debug_region+cell+encrypt $(DUT) $(TB) -l com_$(SEED).log

simulate:
	./simv +plusargs_save +seed = $(SEED) +cycle_num =$(CYCLE_NUM) -l sim_$(SEED).log

#---------------- coverage driven strategy -----------------------------------------
run_cov: compile_cov simulate_cov

compile_cov:
	vcs -debug_acc+all -debug_region+cell+encrypt -cm line+cond+fsm+tgl+branch -lca $(DUT) $(TB) -l com_$(SEED).log

simulate_cov:
	./simv +plusargs_save +seed=$(SEED) +cycle_num =$(CYCLE_NUM) -cm line+cond+fsm+tgl+branch -lca -cm_log cm_$(SEED).log -l sim_$(SEED).log

report_cov: //生成报告
	urg -dir simv.vdb -format both -report coverage

dve_cov: //查看报告
	dve -cov -covdir simv.vdb -lca

#-------------------------clean------------------------------------------------------
clean:
	rm -rf *.log DVEfiles simv simv.daidir *.vpd *.key csrc/ coverage/ simv.vdb/