Fsm serial

In many (older) serial communications protocols, each data byte is sent along with a start bit and a stop bit, to help the receiver delimit bytes from the stream of bits. One common scheme is to use one start bit (0), 8 data bits, and 1 stop bit (1). The line is also at logic 1 when nothing is being transmitted (idle).

在许多(较旧的)串行通信协议中,每一个数据字节与一个起始位和一个停止位一起发送,以帮助接收器从比特流中划分字节.一种常见的方案是使用一个起始位(0),8个数据位和1个停止位(1).当没有传输(空闲)时,线路也位于逻辑1.

Design a finite state machine that will identify when bytes have been correctly received when given a stream of bits. It needs to identify the start bit, wait for all 8 data bits, then verify that the stop bit was correct. If the stop bit does not appear when expected, the FSM must wait until it finds a stop bit before attempting to receive the next byte.

设计一个有限状态机,在给定位流时识别何时正确接收.它需要去识别起始位,等待所以8个数据位,然后验证停止位是正确的.如果停止位没有在预期时出现,则FSM必须等待找到停止位后才能接收下一个字节.

coding:

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output done
); 
	parameter idle = 0,start=1,data=2,stop=3,error=4;
    reg [2:0]state,next_state;
    reg [3:0]cnt;//自定义的计数器cnt,用于计数start和stop之间的位数是否满足1byte
    reg done_r;
   /* always@(*)begin
        if(reset)
            state<=idle;
        else
            state<=next_state;
    end*/
    //transition   组合电路
    always@(*)begin
        case(state)
            idle:next_state=in?idle:start;
            start:next_state=data;
            data:next_state=(cnt==8)?(in?stop:error):data;
            stop:next_state=in?idle:start;
            error:next_state=in?idle:error;
        endcase
    end
    
    
    //state
    always@(posedge clk)begin
        if(reset)
            state<=idle;
        else
            state<=next_state;
    end
    
    //cnt
    always@(posedge clk)begin
        if(reset)
            cnt<=0;
        else
            case(next_state)
                start:cnt<=0;
                data:cnt<=cnt+1;
                default:cnt<=cnt;
            endcase
    end
    
    
    //done_r
    always@(posedge clk)
        case(next_state)
            stop:done_r <=1;
            default:done_r<=0;
        endcase
    
    assign done = done_r;
            
endmodule