Vivado 双口RAM 的调用和实现

1、双口RAM例程

例程1，Altera官方例程，采用寄存器构建双口RAM

moduletrue_dpram_sclk

(

    input [7:0] data_a, data_b,

    input [5:0] addr_a, addr_b,

    input we_a, we_b, clk,

    outputreg [7:0] q_a, q_b

);

    // Declare the RAM variable

    reg [7:0] ram[63:0];

    // Port A

    always @ (posedge clk)

    begin

        if (we_a)

        begin

            ram[addr_a] <= data_a;

            q_a <= data_a;

        end

        else

        begin

            q_a <= ram[addr_a];

        end

    end

    // Port B

    always @ (posedge clk)

    begin

        if (we_b)

        begin

            ram[addr_b] <= data_b;

            q_b <= data_b;

        end

        else

        begin

            q_b <= ram[addr_b];

        end

    end

endmodule

例程2，Xilinx官方例程，采用寄存器构建真双口RAM

// Dual-Port Block RAM with Two Write Ports

// File: rams_16.v

modulev_rams_16 (
        clka,
        clkb,
        ena,
        enb,
        wea,
        web,
        addra,
        addrb,
        dia,
        dib,
        doa,
        dob
);

input clka,clkb,ena,enb,wea,web;

input [9:0] addra,addrb;

input [15:0] dia,dib;

output [15:0] doa,dob;

reg[15:0] ram [1023:0];

reg[15:0] doa,dob;

always @(posedge clka) 
begin if (ena)
    begin

if (wea)

ram[addra] <= dia;

doa <= ram[addra];

end

end

always @(posedge clkb) beginif (enb)

begin

if (web)

ram[addrb] <= dib;

dob <= ram[addrb];

end

end

endmodule

    例程3，该例程是网友博客中的例程[]，代码如下：

moduleTOP(

input USER_CLK

)

`define DLY #1

reg FPGA_Enable=0;

reg[3:0] FPGA_Write_Enable=4'h0;

reg[31:0] FPGA_Address=0;

reg[31:0] FPGA_Write_Data=0;

reg[31:0] FPGA_Read_Data_reg=0;

wire[31:0] FPGA_Read_Data;

reg[10:0] count=0;

always @ (posedge USER_CLK)

begin

 

count <= count +1;

 

if(count<=100)

 

begin

 

FPGA_Enable <=0;

 

FPGA_Write_Enable <=4'h0;

 

end

 

elseif((count <=105)&&(count >100))

 

begin

 

FPGA_Enable <=1;

 

FPGA_Write_Enable <=4'hf;

 

FPGA_Address <= FPGA_Address +4;

 

FPGA_Write_Data <= FPGA_Write_Data +1;

 

end

 

elseif((count <=110)&&(count >105))

 

begin

 

FPGA_Enable <=0;

 

FPGA_Write_Enable <=4'h0;

 

FPGA_Address <=0;

 

FPGA_Write_Data <=0;

 

end

 

elseif((count <=117)&&(count >110))

 

begin

 

FPGA_Enable <=1;

 

FPGA_Write_Enable <=4'h0;

 

FPGA_Read_Data_reg <= FPGA_Read_Data;

 

FPGA_Address <= FPGA_Address +4;

 

end

 

elseif(count ==118)

 

begin

 

FPGA_Enable <=0;

 

count <= count;

 

 

 

end

 

end

 

 

 

BBBByour_instance_name (

 

.clka(USER_CLK), // input clka

 

.ena(FPGA_Enable), // input ena

 

.wea(FPGA_Write_Enable), // input [3 : 0] wea

 

.addra(FPGA_Address), // input [31 : 0] addra

 

.dina(FPGA_Write_Data), // input [31 : 0] dina

 

.douta(FPGA_Read_Data), // output [31 : 0] douta

 

 

 

 

 

.clkb(clkb), // input clkb

 

.enb(enb), // input enb

 

.web(web), // input [3 : 0] web

 

.addrb(addrb), // input [31 : 0] addrb

 

.dinb(dinb), // input [31 : 0] dinb

 

.doutb(doutb) // output [31 : 0] doutb

 

);

 

endmodule