Verilog 编程实验(2)-4位2选1多路选择器的设计与实现

4位2选1多路选择器：

Implementation part:

//////////////////////////////////////////////////////////////////////////////////
module MUX_4bits_2_choose_1(

input wire [3:0]a,
input wire [3:0]b,
input wire s,
output wire [3:0]y
    );
assign y = s? a:b;
endmodule

Simulation part:

module MUX_4bits_2_choose_1_Test2;

    // Inputs
    reg [3:0] a;
    reg [3:0] b;
    reg s;

    // Outputs
    wire [3:0] y;

    // Instantiate the Unit Under Test (UUT)
    MUX_4bits_2_choose_1 uut (
        .a(a), 
        .b(b), 
        .s(s), 
        .y(y)
    );

    initial begin
        // Initialize Inputs
        a = 0;
        b = 0;
        s = 0;

        // Wait 100 ns for global reset to finish
        #100;

        // Add stimulus here
        #200
        a <= 4'b0000;
        b <= 4'b0000;


        #200
        a <= 4'b0010;
        b <= 4'b0000;

        #200
        a <= 4'b1010;
        b <= 4'b0011;

        #200
        a <= 4'b1010;
        b <= 4'b0110;   

    end

endmodule

Simulation Behavioral Model:

RTL Schematic:

欢迎指正—-