信号名 | 位宽 | I/O | 描述 |
clk | 1 | I | 时钟 |
nrst | 1 | I | 全局异步时钟,低电平有效,有效时所有寄存器清零 |
stall | 1 | I | 暂停信号,该信号为1时,寄存器所有值保持不变 |
ren | 1 | I | 读使能,高电平有效 |
radd1/radd2 | 5 | I | 两个读数据端口地址 |
wen | 1 | I | 写使能,高电平有效 |
wadd | 5 | I | 写数据端口地址 |
wdata | 32 | I | 写端口数据 |
rs1/rs2 | 32 | O | 从寄存器堆读出两个操作数 |
general_purpose_register.v
module general_purpose_register(
input clk,
input nrst,
input stall,
input ren,
input [4:0] radd1,
input [4:0] radd2,
input wen,
input [4:0] wadd,
input [31:0] wdata,
output reg [31:0] rs1,
output reg [31:0] rs2
);
reg [31:0] RF [31:0];
always @ (posedge clk or negedge nrst)
begin
if(~nrst)
begin
RF[0] = 32'h0;
RF[1] = 32'h0;
RF[2] = 32'h0;
RF[3] = 32'h0;
RF[4] = 32'h0;
RF[5] = 32'h0;
RF[6] = 32'h0;
RF[7] = 32'h0;
RF[8] = 32'h0;
RF[9] = 32'h0;
RF[10] = 32'h0;
RF[11] = 32'h0;
RF[12] = 32'h0;
RF[13] = 32'h0;
RF[14] = 32'h0;
RF[15] = 32'h0;
RF[16] = 32'h0;
RF[17] = 32'h0;
RF[18] = 32'h0;
RF[19] = 32'h0;
RF[20] = 32'h0;
RF[21] = 32'h0;
RF[22] = 32'h0;
RF[23] = 32'h0;
RF[24] = 32'h0;
RF[25] = 32'h0;
RF[26] = 32'h0;
RF[27] = 32'h0;
RF[28] = 32'h0;
RF[29] = 32'h0;
RF[30] = 32'h0;
RF[31] = 32'h0;
end
if(~stall)
begin
if(wen)
RF[wadd] = wdata;
end
if(ren)
begin
rs1 <= RF[radd1];
rs2 <= RF[radd2];
end
end
endmodule
general_purpose_register_tb.v
module general_purpose_register_tb(
);
reg clk;
reg nrst;
reg stall;
reg ren;
reg [4:0] radd1;
reg [4:0] radd2;
reg wen;
reg [4:0] wadd;
reg [31:0] wdata;
wire [31:0] rs1;
wire [31:0] rs2;
reg [7:0]cnt;
general_purpose_register gpr0(
.clk(clk),
.nrst(nrst),
.stall(stall),
.ren(ren),
.radd1(radd1),
.radd2(radd2),
.wen(wen),
.wadd(wadd),
.wdata(wdata),
.rs1(rs1),
.rs2(rs2)
);
initial
begin
clk = 0;
nrst = 0;
#10
nrst = 1;
stall = 0;
wadd = 0;
radd1 = 0;
radd2 = 0;
wen = 1;
ren = 1; //读使能
for(cnt = 0; cnt < 32; cnt = cnt+1)
begin
#10
wadd = cnt;
wdata = cnt;
end
#10
radd1 = 1;
radd2 = 3;
end
always #5 clk = ~clk;
endmodule