library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity UART_MODULE is
Port ( clk : in STD_LOGIC;
send : in boolean;
data : in STD_LOGIC_VECTOR (7 downto 0);
tx : out STD_LOGIC;
busy : out STD_LOGIC);
end UART_MODULE;
architecture Behavioral of UART_MODULE is
TYPE state_type IS(Idel, Rdy, LoadByte, SendBit);
signal state : state_type;
signal BspClk : STD_LOGIC;
signal BspClkReg : INTEGER RANGE 0 TO 511;
signal tx_data : STD_LOGIC_VECTOR(9 DOWNTO 0);
signal tx_byte_count : INTEGER RANGE 0 TO 15;
begin
PROCESS(clk)
BEGIN
if (RISING_EDGE(clk)) then
BspClkReg <= BspClkReg + 1;
if(BspClkReg = 434) then
BspClkReg <= 0;
BspClk <= NOT BspClk;
end if;
end if;
END PROCESS;
PROCESS(BspClk)
BEGIN
if (RISING_EDGE(BspClk)) then
CASE state IS
WHEN Idel => tx <= '1';
busy <= '0';
tx_byte_count <= tx_byte_count + 1;
if(NOT send) then
state <= Rdy;
end if;
WHEN Rdy => tx_byte_count <= 0;
tx <= '1';
busy <= '1';
state <= LoadByte;
WHEN LoadByte => tx_data <= '1' & data & '0';
tx <= '1';
busy <= '1';
state <= SendBit;
WHEN SendBit => tx <= tx_data(0);
busy <= '1';
tx_data <= TO_STDLOGICVECTOR(TO_BITVECTOR(tx_data) SRL 1);
tx_byte_count <= tx_byte_count + 1;
if(tx_byte_count = 9) then
state <= Idel;
else
state <= SendBit;
end if;
WHEN OTHERS => NULL;
END CASE;
end if;
END PROCESS;
end Behavioral;