如何提取IC验证feature

该文为阅读《Writing Testbenches with SystemVerilog》笔记整理，英文为原文。

提取feature先看 interface，然后看功能，最后看架构的边界场景。

In The Art of Verification 1 , Haque, Michelson and Khan propose using a methodical approach for extracting significant and relevant features to verify by first looking at the interfaces, then the functions, then finally the corner cases implied by the chosen architecture.

I. 对于基于interface 的 feature， 需要考虑以下几点：
1.需要用到哪些transaction
2.transaction 信号的取指范围
3.transaction 的应用flow，比如发送，接收，错误检测，中断处理，配置和状态查询等事务。
4.命令的下发速度，即dut的响应速度
5.dut 可以处理哪些异常
6.该dut interface和其他module 如何交互
7.测试module交互信号是否同步

The interface-based features can be obtained by asking questions such as:
• What transactions must be applied?
• What range of values?
• What sequences of transactions?
• What are the relevant transaction densities?
• What protocol violations should the design be able to sustain?
• What are the relevant interactions between this interface and other interfaces or internal design structures?
• Do transactions on an interface need to be synchronized with those of another interface?

uart(通用异步收发器) interface 相关 feature示例：
1.uart传数据的时候，需要添加断言检查cts信号值是否正确（cts信号是接受方的ready状态，cts为1时，发送方可以发送数据，否则需等待。)

遗留问题：rx/tx上没有这个check，如何工作的？

2.断言检查 uart进行数据传输之前，DTR 信号是否拉起来（DTR信号为1表示数据终端设备ready。ready方可通信。）

断言检查slave uart（数据通讯设备） 发起读操作时，master slave（数据终端设备） 的DTR信号是否拉起来。我们control 是master，通信的外设是slave(有多个)

3.uart只用到 0~4的地址范围，所以需要验证此范围之外的地址是否未被忽略

4.验证在有效地址空间内，是否支持连续的读，写，写读，读写等操作。

遗留问题：写读，读写也不需要等待时间？需要看波形确认

5.验证寄存器的所有bit都可读可写，且不会丢失。

遗留问题：断电丢失？和设计确认

A subset of the interface-based feature list for a Universal Asyn chronous Receiver Transmitter (UART) is shown in Sample 3-1.

1.The Clear-To-Send (CTS) pin must be asserted when the UART can accept a new word to be transmitted via the CPU interface.
2. The Data Terminal Ready (DTR) pin must be asserted when there is a received word ready to be read by the CPU inter- face.
3. Read and write cycles to addresses other than 0 through 4 are ignored.
4. Back-to-back read/read, read/write, write/write and write/ read cycles within the address space are supported.
5. All bits in the configuration registers are readable, writable and non-volatile.

II. 基于功能的feature,需要考虑以下几点：
1.相关功能配置flow
2.数据可能执行哪些转换？（位宽转换，编码进制转换，校验计算，加解密，解压打包，这些功能都是control做）
3.触发各种转换的条件值是否一一对应
4.转换异常的情况有哪些
5.转换后的数据是否传给正确的交互对象
6.哪些场景会影响数据转义，如何解决
7.验证报错机制
8.面对出错，dut是否合理响应

The function-based features can be obtained by asking questions such as:
• What are all the relevant configurations?
• What are the possible transformations that can be performed on the data?
• What are the possible sequences of transformation?
• What are the sensitive data values for triggering transformations?
• What are the sensitive values that affect each transformation?
• Where should the transformed data end up?
• How is the data ordering affected?
• What error detection mechanisms exist and how are they triggered?
• How do error mechanisms report errors?
• What happens to erroneous data?

针对以上问题，提取部分待验证功能如下：
1.数据位首先以最低有效位串行发送和接收。
2.数据字节的发送顺序与写入顺序相同。
3.数据字节的读取顺序与接收顺序相同。
4.根据配置的模式生成奇偶校验。
5.根据配置模式检查奇偶校验。

1.Data bits are sent and received serially with the least significant bit first.
2. Data bytes are sent in the same order in which they were written.
3. Data bytes are read in the same order in which they were received.
4. Parity is generated according to configured mode.
5. Parity is checked according to configured mode.

III. 基于架构的feature,需要考虑以下几点：
1.是否存在overflow（已经满了还想写）或underflow（已经读完了还想读）情况，会发生什么。项目不存在underflow; buffer满了之后不会给slave发读命令。会先报中断，等fw处理之后才继续发读命令。
2.有哪些资源瓶颈（如：带宽瓶颈，缓冲区大小瓶颈，中断处理瓶颈，硬件瓶颈（内存，处理器等不可以验））
3.多个请求同时发生如何响应？
4.不同转换路径会相互影响吗？

遗留问题：我理解是全双工的读写操作，两个数据流独立，是否会有干扰，怎么发同步命令，波形确认

The architecture-based features can be obtained by asking questions such as:
• Can I overflow or underflow a buffer? If so, what should happen?
• Where are the resource bottlenecks?
• Can multiple requests for these resources occur at the same time?
• Can a transformation path affect, prevent or block another?