vhdl数字逻辑2

4位二进制同步计数器（异步清除）CT74161

 

 

LIBRARY IEEE;

USEIEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY CT74161 IS

      PORT{LDN,D3,D2,D1,D0,CP,DRN,EP,ET:INSTD_LOGIC;

                 Q3,Q2,Q1,Q0,OC:BUFFERSTD_LOGIC};

END  CT74161;

ARCHITECTURE oneOF CT74161 IS

      SIGNAL ENA:STD_LOGIC_VECTOR(1 DOWNTO 0);

      SIGNAL D_SIGNAL:STD_LOGIC_VECTOR(3 DOWNTO0);

      SIGNAL Q_SIGNAL:STD_LOGIC_VECTOR(3 DOWNTO0);

BEGIN

PROCESS(LDN,D3,D2,D1,D0,CP,CRN,EP,ET)

 BEGIN   

      ENA<=(EP&ET);

      D_SIGNEL <=(D3&D2&D1&D0);

      IF (CRN = ‘0’) THEN Q_SIGNAL <= “0000”;

       ELSE IF CP’EVENT AND CP = ‘1’ THEN

           IF(LDN=’0’) THEN Q_SIGNAL <=D_SIGNAL;

            ELSIF(ENA = “11”) THEN

                      Q_SIGNAL < = Q_SIGNAL +1;

            ELSE

                      Q_SIGNAL < = Q_SIGNAL;

            END IF;

           END IF;

END IF;

Q3 <= Q_SIGNAL(3);

Q2 <= Q_SIGNAL(2);

Q1 <= Q_SIGNAL(1);

Q0 <= Q_SIGNAL(0);

OC <= ET AND Q3 AND Q2 AND Q1 AND Q0;

  END PROCESS;

END one;