Cadence disign entry hdl常见错误及解决办法:
错误1:WARNING(SPCOCN-2106): Errors and warnings were found while updating connectivity of pages due to port addition. Check the following markers file for errors and warnings:temp/ppc_j0.sch_1.mkr
解决办法:重新生成symbol.
错误2: ERROR(SPCODD-563): Following blocks have netlisting errors. Fix them in ~
Design Entry HDL before packaging: mfi_j0
INFO(SPCOPK-1441): 1 errors detected
INFO(SPCOPK-1444): No warnings detected
INFO(SPCOPK-1448): Use Tools->Markers->Packager in ConceptHDL to highlight ins~
tances for the errors/warnings reported.
解决办法:重新生成symbol.
错误3: ERROR(SPCOPK-1149): Found a hard location ‘J0_DSP2’ for
Schematic instance: @VPX_BACKPLANES_LIB.TOP_ALL_ALL(SCH_1):PAGE1_I4@VP~
X_BACKPLANES_LIB.DSP_J0(SCH_1):PAGE1_I13@SCHEMATIC_LIBRARY_LIB.VPX_J0(CHIPS) (~
MODULE: DSP_J0; PART: VPX_J0)
Physical Path: @vpx_backplanes_lib.top_all_all(sch_1):page1_i4@vpx_bac~
kplanes_lib.dsp_j0(sch_1):page1_i13@schematic_library_lib.vpx_j0(chips)
A hard location on instances of different physical part names is not s~
upported. Correct the location for the appropriate instance(s).
解决办法:导致错误的原因可能是,在底层同一个底层中,用了不同的位号,例如:我在DSP1实例的底层中的一个电阻R的位号用的是DSP1_GAP,在DSP2实例的底层中的一个电阻R的位号用的是DSP2_GAP,实际上两个实例的底层是同一个电路,这样就有冲突了。导致错误的原因还可能是原理图中有重名的位号,有可能是copy all时一起复制的,后期没有修改。改正就好。
前言:
基本知识:AMS Simulator使用AMS模拟器进行模拟、数字和混合信号模拟。
基本知识点
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Setup - Application Mode - General Edit
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鼠标放置显示图层的设置user preferences打开,在Setup - Datatip Customization 设置显示的具体内容。
3.添加密码File – Properties