verilog =与<=的区别:
module test(
input wire clk_test
);
reg a=0,b=0,c=0;
always @( posedge clk_test )
begin
a=1;
b=a;
c=b;
end
reg a1=0,b1=0,c1=0;
always @( posedge clk_test )
begin
a1<=1;
b1<=a1;
c1<=b1;
end
endmodule
verilog =与<=的区别:
module test(
input wire clk_test
);
reg a=0,b=0,c=0;
always @( posedge clk_test )
begin
a=1;
b=a;
c=b;
end
reg a1=0,b1=0,c1=0;
always @( posedge clk_test )
begin
a1<=1;
b1<=a1;
c1<=b1;
end
endmodule