代码在这:github代码
修改管脚后直接运行
通过FPGA管脚直接连接hdmi接口,输出彩条如下
工程如下:
其中主模块如下
//--------------------------------------------------
clk_wiz_0 clk125m
(
// Clock out ports
.clk_out1(clk_125M), // output clk_out1
// Status and control signals
.reset(0), // input reset
.locked(), // output locked
// Clock in ports
.clk_in1_p(sysclk_p), // input clk_in1_p
.clk_in1_n(sysclk_n)); // input clk_in1_n
//-----------------------------------------------------
color_bar color_bar_inst(
.clk (video_clk),
.rst (1'b0),
.hs (video_hs),
.vs (video_vs),
.de (video_de),
.rgb_r (video_r),
.rgb_g (video_g),
.rgb_b (video_b)
);
//----------------------------------------------
video_pll video_pll_inst(
.clk_in1 (clk_125M),
.clk_out1 (video_clk),
.clk_out2 (video_clk_5x),
.reset (1'b0),
.locked ()
);
//--------------------------------------------------
hdmi_disp hdmi_disp_inst (
// DVI 1.0 TMDS video interface
.TMDS_Clk_p (TMDS_clk_p),
.TMDS_Clk_n (TMDS_clk_n),
.TMDS_Data_p (TMDS_data_p),
.TMDS_Data_n (TMDS_data_n),
//Auxiliary signals
.aRst (1'b0), //asynchronous reset; must be reset when RefClk is not within spec
.aRst_n (1'b1), //-asynchronous reset; must be reset when RefClk is not within spec
// Video in
.vid_pData ({video_r,video_b,video_g}),
.vid_pVDE (video_de),
.vid_pHSync (video_hs),
.vid_pVSync (video_vs),
.PixelClk (video_clk),
.SerialClk (video_clk_5x)// 5x PixelClk
);
彩条代码如下:
always@(posedge clk or posedge rst)
begin
if(rst)
begin
hs_reg_d0 <= 1'b0;
vs_reg_d0 <= 1'b0;
video_active_d0 <= 1'b0;
end
else
begin
hs_reg_d0 <= hs_reg;
vs_reg_d0 <= vs_reg;
video_active_d0 <= video_active;
end
end
always@(posedge clk or posedge rst)
begin
if(rst)
h_cnt <= 12'd0;
else if(h_cnt == H_TOTAL - 1)//行计数器到最大值清零
h_cnt <= 12'd0;
else
h_cnt <= h_cnt + 12'd1;
end
always@(posedge clk or posedge rst)
begin
if(rst)
active_x <= 12'd0;
else if(h_cnt >= H_FP + H_SYNC + H_BP - 1)//计算图像的x坐标
active_x <= h_cnt - (H_FP[11:0] + H_SYNC[11:0] + H_BP[11:0] - 12'd1);
else
active_x <= active_x;
end
always@(posedge clk or posedge rst)
begin
if(rst)
v_cnt <= 12'd0;
else if(h_cnt == H_FP - 1)//在行数计算器为H_FP - 1的时候场计数器+1或清零
if(v_cnt == V_TOTAL - 1)//场计数器到最大值了,清零
v_cnt <= 12'd0;
else
v_cnt <= v_cnt + 12'd1;//没到最大值,+1
else
v_cnt <= v_cnt;
end
always@(posedge clk or posedge rst)
begin
if(rst)
hs_reg <= 1'b0;
else if(h_cnt == H_FP - 1)//行同步开始了...
hs_reg <= 1'b1;
else if(h_cnt == H_FP + H_SYNC - 1)//行同步这时候要结束了
hs_reg <= 1'b0;
else
hs_reg <= hs_reg;
end
always@(posedge clk or posedge rst)
begin
if(rst)
h_active <= 1'b0;
else if(h_cnt == H_FP + H_SYNC + H_BP - 1)
h_active <= 1'b1;
else if(h_cnt == H_TOTAL - 1)
h_active <= 1'b0;
else
h_active <= h_active;
end
always@(posedge clk or posedge rst)
begin
if(rst)
vs_reg <= 1'd0;
else if((v_cnt == V_FP - 1) && (h_cnt == H_FP - 1))
vs_reg <= 1'b1;
else if((v_cnt == V_FP + V_SYNC - 1) && (h_cnt == H_FP - 1))
vs_reg <= 1'b0;
else
vs_reg <= vs_reg;
end
always@(posedge clk or posedge rst)
begin
if(rst)
v_active <= 1'd0;
else if((v_cnt == V_FP + V_SYNC + V_BP - 1) && (h_cnt == H_FP - 1))
v_active <= 1'b1;
else if((v_cnt == V_TOTAL - 1) && (h_cnt == H_FP - 1))
v_active <= 1'b0;
else
v_active <= v_active;
end
always@(posedge clk or posedge rst)
begin
if(rst)
begin
rgb_r_reg <= 8'h00;
rgb_g_reg <= 8'h00;
rgb_b_reg <= 8'h00;
end
else if(video_active)
if(active_x == 12'd0)
begin
rgb_r_reg <= WHITE_R;
rgb_g_reg <= WHITE_G;
rgb_b_reg <= WHITE_B;
end
else if(active_x == (H_ACTIVE/8) * 1)
begin
rgb_r_reg <= YELLOW_R;
rgb_g_reg <= YELLOW_G;
rgb_b_reg <= YELLOW_B;
end
else if(active_x == (H_ACTIVE/8) * 2)
begin
rgb_r_reg <= CYAN_R;
rgb_g_reg <= CYAN_G;
rgb_b_reg <= CYAN_B;
end
else if(active_x == (H_ACTIVE/8) * 3)
begin
rgb_r_reg <= GREEN_R;
rgb_g_reg <= GREEN_G;
rgb_b_reg <= GREEN_B;
end
else if(active_x == (H_ACTIVE/8) * 4)
begin
rgb_r_reg <= MAGENTA_R;
rgb_g_reg <= MAGENTA_G;
rgb_b_reg <= MAGENTA_B;
end
else if(active_x == (H_ACTIVE/8) * 5)
begin
rgb_r_reg <= RED_R;
rgb_g_reg <= RED_G;
rgb_b_reg <= RED_B;
end
else if(active_x == (H_ACTIVE/8) * 6)
begin
rgb_r_reg <= BLUE_R;
rgb_g_reg <= BLUE_G;
rgb_b_reg <= BLUE_B;
end
else if(active_x == (H_ACTIVE/8) * 7)
begin
rgb_r_reg <= BLACK_R;
rgb_g_reg <= BLACK_G;
rgb_b_reg <= BLACK_B;
end
else
begin
rgb_r_reg <= rgb_r_reg;
rgb_g_reg <= rgb_g_reg;
rgb_b_reg <= rgb_b_reg;
end
else
begin
rgb_r_reg <= 8'h00;
rgb_g_reg <= 8'h00;
rgb_b_reg <= 8'h00;
end
end