ov13855在rk3588上设备树配置及显示图像偏绿

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已于 2024-07-24 11:21:08 修改

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本文链接：https://blog.csdn.net/qq_34843220/article/details/140500215

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参考: https://www.cnblogs.com/arnoldlu/p/18107354

RK3588-Camera:MIPI-CSI及ISP调试之通路解析_rk3588 isp-CSDN博客

硬件框架

1. 外部MIPI/LVDS/DVP Camera采集数据，最多支持7路输入(6 MIPI + 1 DVP)

2.MIPI接口：

CSI-2是MIPI针对摄像头芯片接口协议。

D/C-PHY同时支持D-PHY和C-PHY。

D-PHY支持1路4Lane，或者2路2Lane组合

3.DVP接口或称为Camera并口，一般支持BT601/BT656/BT1120数据的传输

4. VICAP负责从DVP/MIPI接收数据，将数据通过AXI存入内存，或者直接送到ISP

5.ISP对Camera Sensor输出的图像信号进行后处理，最多支持4路数据源输入。有两个isp. VICAP数据到ISP支持直通和回读两种模式：

直通：指数据经过VICAP采集，直接发送给ISP处理，不存储到DDR。需要注意的是hdr直通时，只有短帧是真正的直通，长帧需要存在DDR，ISP再从DDR读取。

回读：指数据经过VICAP采集到DDR，应用获取到数据后，将buffer地址推送给ISP，ISP再从DDR获取图像数据。

6.FEC(Fish Eye Correction)负责鱼眼校正

7.以OV13850为例，详细解释数据链路：

OV13850由IC接口进行配置，需要MIPI 4 Lane将数据送到MIPI DPHY。

DPHY0 csi2_dphy0作为输入端，将数据送到CSI HOST2。

VICAP虚拟出多个设备，通过rkcif_mipi_lvds2设备接收数据，通过rkcif_mipi_lvds2_sditf输出到ISP0。

ISOP0虚拟出4个设备，通过rkisp0_vir0接收数据进行处理。

8.以OV13850为例，整个软硬件框架分为：

硬件层：包含I2C Master、OV13850、DPHY、CSI2、VICAP、ISP等。

内核驱动层：I2C Master Driver、OV13850 Driver、DPHY Driver、CSI2 Host Driver、RKCIF Driver、ISP Driver、v4l2 Subsystem、I2C Subsystem、Media Subsystem等。

用户层：基于/dev/videoX设备的用户程序以及测试程序等

1. rk3588支持两个dcphy，节点名称分别为csi2_dcphy0/csi2_dcphy1。每个dcphy硬件支持RX/TX同时使用，对于camera输入使用的是RX。支持DPHY/CPHY协议复用；需要注意的是同一个dcphy的TX/RX只
能同时使用DPHY或同时使用CPHY。其他dcphy参数请查阅rk3588数据手册。
2. rk3588支持2个dphy硬件，这里我们称之为dphy0_hw/dphy1_hw，两个dphy硬件都可以工作在full
mode 和split mode两种模式下。
    1. dphy0_hw
        1. full mode：节点名称使用csi2_dphy0，最多支持4 lane。
        2. split mode： 拆分成2个phy使用，分别为csi2_dphy1（使用0/1 lane）、csi2_dphy2(使用2/3 lane)，每个phy最多支持2 lane。
        3. 当dphy0_hw使用full mode时，链路需要按照csi2_dphy1这条链路来配置，但是节点名称csi2_dphy1需要修改为csi2_dphy0，软件上是通过phy的序号来区分phy使用的模式。
    2. dphy1_hw
        1. full mode：节点名称使用csi2_dphy3，最多支持4 lane。
        2. split mode： 拆分成2个phy使用，分别为csi2_dphy4（使用0/1 lane）、csi2_dphy5(使用2/3 lane)，每个phy最多支持2 lane。
    3. 当dphy1_hw使用full mode时，链路需要按照csi2_dphy4这条链路来配置，但是节点名称csi2_dphy4需要修改为csi2_dphy3，软件上是通过phy的序号来区分phy使用的模式。
3. 使用上述mipi phy节点，需要把对应的物理节点配置上。（csi2_dcphy0_hw/csi2_dcphy1_hw/csi2_dphy0_hw/csi2_dphy1_hw）
4. 每个mipi phy都需要一个csi2模块来解析mipi协议，节点名称分别为mipi0_csi2~mipi5_csi2。
5. rk3588所有camera数据都需要通过vicap，再链接到isp。rk3588仅支持一个vicap硬件，这个vicap支持同时输入6路mipi phy，及一路dvp数据，所以我们将vicap分化成
rkcif_mipi_lvds~rkcif_mipi_lvds5、rkcif_dvp等7个节点，各个节点的绑定关系需要严格按照框图的节点序号配置。
6. 每个vicap节点与isp的链接关系，通过对应虚拟出的XXX_sditf来指明链接关系。
7. rk3588支持2个isp硬件，每个isp设备可虚拟出多个虚拟节点，软件上通过回读的方式，依次从ddr读取每一路的图像数据进isp处理。对于多摄方案，建议将数据流平均分配到两个isp上。
8. 直通与回读模式：
    1. 直通：指数据经过vicap采集，直接发送给isp处理，不存储到ddr。需要注意的是hdr直通时，只有短帧是真正的直通，长帧需要存在ddr，isp再从ddr读取。
    2. 回读：指数据经过vicap采集到ddr，应用获取到数据后，将buffer地址推送给isp，isp再从ddr获取图像数据。
    3. 再dts配置时，一个isp硬件，如果只配置一个虚拟节点，默认使用直通模式，如果配置了多个虚拟节点默认使用回读模式。


csi2_dphy0_hw
csi2_dphy1_hw


csi2_dphy0  
csi2_dphy1    
csi2_dphy2
csi2_dphy3
csi2_dphy4
csi2_dphy5


csi2_dcphy0
csi2_dcphy1


mipi0_csi2
mipi1_csi2
mipi2_csi2
mipi3_csi2
mipi4_csi2
mipi5_csi2


rkcif_dvp
rkcif_dvp_sditf

rkcif_mipi_lvds
rkcif_mipi_lvds_sditf
rkcif_mipi_lvds_sditf_vir1
rkcif_mipi_lvds_sditf_vir2
rkcif_mipi_lvds_sditf_vir3

rkcif_mipi_lvds1
rkcif_mipi_lvds1_sditf
rkcif_mipi_lvds1_sditf_vir1
rkcif_mipi_lvds1_sditf_vir2
rkcif_mipi_lvds1_sditf_vir3

rkcif_mipi_lvds2  
rkcif_mipi_lvds2_sditf 
rkcif_mipi_lvds2_sditf_vir1
rkcif_mipi_lvds2_sditf_vir2
rkcif_mipi_lvds2_sditf_vir3

rkcif_mipi_lvds3
rkcif_mipi_lvds3_sditf
rkcif_mipi_lvds3_sditf_vir1
rkcif_mipi_lvds3_sditf_vir2
rkcif_mipi_lvds3_sditf_vir3

rkcif_mipi_lvds4
rkcif_mipi_lvds4_sditf
rkcif_mipi_lvds4_sditf_vir1
rkcif_mipi_lvds4_sditf_vir2
rkcif_mipi_lvds4_sditf_vir3


rkcif_mipi_lvds5
rkcif_mipi_lvds5_sditf
rkcif_mipi_lvds5_sditf_vir1
rkcif_mipi_lvds5_sditf_vir2
rkcif_mipi_lvds5_sditf_vir3

isp0_mmu
rkisp0
rkisp0_vir0
rkisp0_vir1
rkisp0_vir2
rkisp0_vir3

isp1_mmu
rkisp1
rkisp1_vir0
rkisp1_vir1
rkisp1_vir2
rkisp1_vir3

fec0_mmu
rkispp0
rkispp0_vir0


fec1_mmu
rkispp1
rkispp1_vir0

进行实战

设备树中整体配置可以参考其它设备树, 主要配置i2c中ov13855配置

ov13855摄像头使用的是图中画红框部分

数据流 mipi camera ---> csi2_dphy0 ---> mipi2_csi2 ---> rkcif_mipi_lvds2 ---> rkcif_mipi_lvds2_sditf ---> rkisp0_vir0

1. i2c配置

2. 四个电源配置

由于硬件设计将四个电源直供, 不需要使用gpio来进行控制所以注释掉了

3. reset-gpios和pwdn-gpios配置

4.MIPI_CAM0_CLK配置

当驱动日志显示下图表示i2c可以通信了并可以读取到chip id了, 但是报could not set init registers 说明mipi_cam0_clk没有配置好

5.mipi_cam0_clk的主要配置

这里最主要的是clocks = <&cru CLK_MIPI_CAMARAOUT_M3> ; CLK_MIPI_CAMARAOUT_M3和mipim0_camera3_clk对应上, mipim0_camera3_clk使用的是gpio1_d6(gpio1_30)

根据Rockchip_Developer_Guide_Gpio_Output_Clocks_CN.pdf里面中clk和gpio的对照

5. 整体设备树


// mipi camera ---> csi2_dphy0 ---> mipi2_csi2 ---> rkcif_mipi_lvds2 ---> rkcif_mipi_lvds2_sditf ---> rkisp0_vir0
 

 /{
     vcc_mipidphy0: vcc-mipidphy0-regulator {
        compatible = "regulator-fixed";
        gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;
        pinctrl-names = "default";
        pinctrl-0 = <&mipidphy0_pwr>;
        regulator-name = "vcc_mipidphy0";
        enable-active-high;
        regulator-boot-on;
    };
 };


&i2c3 {
    status = "okay";
    pinctrl-names = "default";
      pinctrl-0 = <&i2c3m0_xfer>;
    ov13855_dph0: ov13855-dph0@10 {
        compatible = "ovti,ov13855";
        status = "okay";
        reg = <0x10>;
        clocks = <&cru CLK_MIPI_CAMARAOUT_M3>;
        clock-names = "xvclk";
        power-domains = <&power RK3588_PD_VI>;
        pinctrl-names = "default";
        pinctrl-0 = <&mipim0_camera3_clk>; 
        rockchip,grf = <&sys_grf>;
        reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
        pwdn-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>;
        //avdd-supply = <&vcc_mipidphy0>;
        rockchip,camera-module-index = <1>;
        rockchip,camera-module-facing = "front";
        rockchip,camera-module-name = "CMK-OT2016-FV1";
        rockchip,camera-module-lens-name = "default";
        port {
            ov13855_dphy0_out: endpoint {
                remote-endpoint = <&mipi_in_dphy0_ov13855>;
                data-lanes = <1 2 3 4>;
            };
        };
    };
};



定义了DPHY的硬件信息
&csi2_dphy0_hw {
    status = "okay";
};

//定义所使用的硬件DPHY资源：csi2_dphy0_hw
//定义了Media Graph上下游：port@0作为Sink Pad，是MIPI Camera；port@1作为Source Pad，是CSI2 Host
&csi2_dphy0 {
    status = "okay";
    ports {
        #address-cells = <1>;
        #size-cells = <0>;
        port@0 {
            reg = <0>;
            #address-cells = <1>;
            #size-cells = <0>;
            mipi_in_dphy0_ov13855: endpoint@1 {
                reg = <1>;
                remote-endpoint = <&ov13855_dphy0_out>;
                data-lanes = <1 2 3 4>;
            };
        };
        port@1 {
            reg = <1>;
            #address-cells = <1>;
            #size-cells = <0>;
            csidphy0_out: endpoint@0 {
                reg = <0>;
                remote-endpoint = <&mipi2_csi2_input>;
            };
        };
    };
    
};



//CSI Host的DTS配置和初始化
&mipi2_csi2 {
    status = "okay";
    ports {
        #address-cells = <1>;
        #size-cells = <0>;
        port@0 {
            reg = <0>;
            #address-cells = <1>;
            #size-cells = <0>;
            mipi2_csi2_input: endpoint@1 {
                reg = <1>;
                remote-endpoint = <&csidphy0_out>;
            };
        };
        port@1 {
            reg = <1>;
            #address-cells = <1>;
            #size-cells = <0>;
            mipi2_csi2_output: endpoint@0 {
                reg = <0>;
                remote-endpoint = <&cif_mipi_in2>;
            };
        };
    };
};


//RKCIF对应的硬件模块为VICAP，负责从DVP/MIPI获取数据并存入内存
//匹配"rockchip,rkcif-mipi-lvds"进行  
&rkcif {
    status = "okay";
};

//选用IOMMU作为RKCIF的MMU
&rkcif_mmu {
    status = "okay";
};

//rkcif_mipi_lvds2作为VICAP的其中一个通道，支持MIPI/LVDS数据搬运
//对应的应将为rkcif，使用iommu作为MMU
//Sink Pad来自于CSI2 Host的mipi2_csi2_output
&rkcif_mipi_lvds2 {
    status = "okay";

    port {
        cif_mipi_in2: endpoint {
            remote-endpoint = <&mipi2_csi2_output>;
        };
    };
};

//rkcif_mipi_lvds2_sditf是基于rkcif_mipi_lvds2虚拟出来的设备，指明和ISP的链路关系, 仅包含一个Source Pad到ISP 
&rkcif_mipi_lvds2_sditf {
    status = "okay";

    port {
        mipi_lvds_sditf: endpoint {
            remote-endpoint = <&isp0_vir0>;
        };
    };
};


//ISP的dts配置和初始化,rkisp0是硬件设备节点
&rkisp0 {
    status = "okay";
};

&isp0_mmu {
    status = "okay";
};

//一个ISP硬件可以虚拟出4个虚拟设备。rkisp_vir0即是ISP硬件设备的虚拟设备
&rkisp0_vir0 {
    status = "okay";
    port {
        #address-cells = <1>;
        #size-cells = <0>;
        isp0_vir0: endpoint@0 {
            reg = <0>;
            remote-endpoint = <&mipi_lvds_sditf>;
        };
    };
};

&pinctrl {
    cam {
        mipidphy0_pwr: mipidphy0-pwr {
            rockchip,pins =
                /* camera power en */
                <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
        };    
    };
};

6. 对应的驱动

compatible = "rockchip,rk3588-cif";  kernel/drivers/media/platform/rockchip/cif/hw.c
compatible = "rockchip,iommu-v2";    kernel/drivers/iommu/rockchip-iommu.c
compatible = "ovti,ov13855";       kernel/drivers/media/i2c/ov13855.c
compatible = "ovti,os04a10";      kernel/drivers/media/i2c/os04a10.c
compatible = "rockchip,rk3588-csi2-dphy-hw";  kernel/drivers/phy/rockchip/phy-rockchip-csi2-dphy-hw.c
compatible = "rockchip,rk3568-csi2-dphy";  kernel/drivers/phy/rockchip/phy-rockchip-csi2-dphy.c
compatible = "rockchip,rk3588-mipi-csi2";  kernel/drivers/media/platform/rockchip/cif/mipi-csi2.c
compatible = "rockchip,rkcif-mipi-lvds";  kernel/drivers/media/platform/rockchip/cif/dev.c
compatible = "rockchip,rkcif-sditf";  kernel/drivers/media/platform/rockchip/cif/subdev-itf.c
compatible = "rockchip,rk3588-rkisp"; kernel/drivers/media/platform/rockchip/isp/hw.c
compatible = "rockchip,iommu-v2";  kernel/drivers/iommu/rockchip-iommu.c
compatible = "rockchip,rkisp-vir"; kernel/drivers/media/platform/rockchip/isp/dev.c

ov13855摄像头显示偏绿

原因是图像没有经过isp处理, rkisp驱动版本和系统程序rkaiq版本要对应

系统程序rkaiq来自camera_engine_rkaiq_rk3588_arm64.deb, 源码来自 SDK/external/camera_engine_rkaiq/rkaiq_tool_server

查看系统程序rkaiq运行状态: systemctl status rkaiq_3A.service

查看系统程序rkaiq日志: journalctl -u rkaiq_3A.service

查看rkisp驱动版本: dmesg | grep "rkisp driver version"

查看系统程序rkaiq版本: journalctl -u rkaiq_3A.service | grep -B 4 "VERSION INFOS END"

注意: 只要设备树配置的mipi csi并且要接上mipi设备, rkaiq_3A_server才会正常后台运行

以下版本对应是ok的

当kernel是5.10.110
rkisp驱动版本: 
    rkisp rkisp0-vir0: rkisp driver version: v02.02.01
程序rkaiq版本:
     ************************** VERSION INFOS **************************
     version release date: 2023-07-06
          AIQ:       AIQ v5.0x1.3
        IQ PARSER:       Calib v1.4.8,magicCode:1170944
    ************************ VERSION INFOS END ************************


当kernel是5.10.198
rkisp驱动版本: 
    rkisp rkisp0-vir0: rkisp driver version: v02.04.00
程序rkaiq版本:
     ************************** VERSION INFOS **************************
     version release date: 2023-10-23
              AIQ:       AIQ v5.0x4.1
     ************************ VERSION INFOS END ************************
    
若是版本不对应程序rkaiq启动失败
若是设备树没设置好程序rkaiq启动失败(可以用相机或者guvcview打开看看)
若是设备树设置好了但没插入mipi摄像头程序rkaiq启动失败


抓到的图颜色不对，亮度也明显偏暗或偏亮
    需要根据Sensor分情况：
    1. Sensor是RAW RGB的输出，如RGGB、BGGR等，需要3A正常跑起来。可以参考4 3A相关 3A 确认正常在跑时，请再次检查解析/显示图像时使用的格式是否正确，uv分量有没有弄反。
    2. Sensor是yuv输出，或RGB如RGB565、RGB888，此时ISP处于bypass状态，如果颜色不对，请确认sensor的输出格式有没有配置错误，uv分量有没有弄反。确认无误时，
    - 建议联系Sensor原厂
    - 如果亮度明显不对，请联系Sensor原厂
参考: Rockchip_Trouble_Shooting_Linux4.4_Camera_CN.pdf



//使用gstreamer打开video11
gst-launch-1.0 v4l2src device=/dev/video11 ! video/x-raw,format=NV12,width=800,height=600, framerate=30/1 ! fpsdisplaysink


程序rkaiq  ===> /usr/bin/rkaiq_3A_server
RKISP Tuner工具 ===> /usr/bin/rkaiq_tool_server

参考: 
Rockchip_Trouble_Shooting_Linux4.4_Camera_CN.pdf
Rockchip_IQ_Tools_Guide_v2.0.6_CN.pdf
https://blog.csdn.net/weixin_45278799/article/details/139620800
https://blog.csdn.net/Dada_ping/article/details/132002262
https://github.com/mfkiwl/rk-open-docs/blob/master/CAMERA/Rockchip_Developer_Guide_Linux4.4_Camera_CN.md
http://wiki.neardi.com/wiki/linux_guide/zh_CN/docs/tool/tool_tuner.html

mipi csi涉及到的设备树

rkcif: rkcif@fdce0000 {
  compatible = "rockchip,rk3588-cif";
  reg = <0x0 0xfdce0000 0x0 0x800>;
  iommus = <&rkcif_mmu>;
  ...
}

rkcif_mmu: iommu@fdce0800 {
  compatible = "rockchip,iommu-v2";
  reg = <0x0 0xfdce0800 0x0 0x100>,
        <0x0 0xfdce0900 0x0 0x100>;
  interrupts = <0 113 4>;
  ...
}

-------------------------------------------

 mipi0_csi2: mipi0-csi2@fdd10000 {
  compatible = "rockchip,rk3588-mipi-csi2";
  reg = <0x0 0xfdd10000 0x0 0x10000>;
  reg-names = "csihost_regs";
  ..
 }
  
 mipi1_csi2: mipi1-csi2@fdd20000 {
  compatible = "rockchip,rk3588-mipi-csi2";
  reg = <0x0 0xfdd20000 0x0 0x10000>;
  reg-names = "csihost_regs";
  ...
 }
  
 mipi2_csi2: mipi2-csi2@fdd30000 {
  compatible = "rockchip,rk3588-mipi-csi2";
  reg = <0x0 0xfdd30000 0x0 0x10000>;
  reg-names = "csihost_regs";
  ...
 }
  
 mipi3_csi2: mipi3-csi2@fdd40000 {
  compatible = "rockchip,rk3588-mipi-csi2";
  reg = <0x0 0xfdd40000 0x0 0x10000>;
  reg-names = "csihost_regs";
  ...
 }

-------------------------------------------

 csi2_dphy0: csi2-dphy0 {
  compatible = "rockchip,rk3568-csi2-dphy";
  rockchip,hw = <&csi2_dphy0_hw>;
  status = "disabled";
 };


 csi2_dphy1: csi2-dphy1 {
  compatible = "rockchip,rk3568-csi2-dphy";
  rockchip,hw = <&csi2_dphy0_hw>;
  status = "disabled";
 };


 csi2_dphy2: csi2-dphy2 {
  compatible = "rockchip,rk3568-csi2-dphy";
  rockchip,hw = <&csi2_dphy0_hw>;
  status = "disabled";
 };

 csi2_dphy0_hw: csi2-dphy0-hw@fedc0000 {
  compatible = "rockchip,rk3588-csi2-dphy-hw";
  reg = <0x0 0xfedc0000 0x0 0x8000>;
  ...
 }

-------------------------------------------


 rkcif_mipi_lvds: rkcif-mipi-lvds {
  compatible = "rockchip,rkcif-mipi-lvds";
  rockchip,hw = <&rkcif>;
  iommus = <&rkcif_mmu>;
  status = "disabled";
 };

 rkcif_mipi_lvds_sditf: rkcif-mipi-lvds-sditf {
  compatible = "rockchip,rkcif-sditf";
  rockchip,cif = <&rkcif_mipi_lvds>;
  status = "disabled";
 };

 rkcif_mipi_lvds_sditf_vir1: rkcif-mipi-lvds-sditf-vir1 {
  compatible = "rockchip,rkcif-sditf";
  rockchip,cif = <&rkcif_mipi_lvds>;
  status = "disabled";
 };

 rkcif_mipi_lvds_sditf_vir2: rkcif-mipi-lvds-sditf-vir2 {
  compatible = "rockchip,rkcif-sditf";
  rockchip,cif = <&rkcif_mipi_lvds>;
  status = "disabled";
 };

 rkcif_mipi_lvds_sditf_vir3: rkcif-mipi-lvds-sditf-vir3 {
  compatible = "rockchip,rkcif-sditf";
  rockchip,cif = <&rkcif_mipi_lvds>;
  status = "disabled";
 };

-------------------------------------------

 rkcif_mipi_lvds1: rkcif-mipi-lvds1 {
  compatible = "rockchip,rkcif-mipi-lvds";
  rockchip,hw = <&rkcif>;
  iommus = <&rkcif_mmu>;
  status = "disabled";
 };

 rkcif_mipi_lvds1_sditf: rkcif-mipi-lvds1-sditf {
  compatible = "rockchip,rkcif-sditf";
  rockchip,cif = <&rkcif_mipi_lvds1>;
  status = "disabled";
 };

 rkcif_mipi_lvds1_sditf_vir1: rkcif-mipi-lvds1-sditf-vir1 {
  compatible = "rockchip,rkcif-sditf";
  rockchip,cif = <&rkcif_mipi_lvds1>;
  status = "disabled";
 };

 rkcif_mipi_lvds1_sditf_vir2: rkcif-mipi-lvds1-sditf-vir2 {
  compatible = "rockchip,rkcif-sditf";
  rockchip,cif = <&rkcif_mipi_lvds1>;
  status = "disabled";
 };

 rkcif_mipi_lvds1_sditf_vir3: rkcif-mipi-lvds1-sditf-vir3 {
  compatible = "rockchip,rkcif-sditf";
  rockchip,cif = <&rkcif_mipi_lvds1>;
  status = "disabled";
 };

-------------------------------------------

rkcif_mipi_lvds2: rkcif-mipi-lvds2 {
  compatible = "rockchip,rkcif-mipi-lvds";
  rockchip,hw = <&rkcif>;
  iommus = <&rkcif_mmu>;
  status = "disabled";
 };

 rkcif_mipi_lvds2_sditf: rkcif-mipi-lvds2-sditf {
  compatible = "rockchip,rkcif-sditf";
  rockchip,cif = <&rkcif_mipi_lvds2>;
  status = "disabled";
 };

 rkcif_mipi_lvds2_sditf_vir1: rkcif-mipi-lvds2-sditf-vir1 {
  compatible = "rockchip,rkcif-sditf";
  rockchip,cif = <&rkcif_mipi_lvds2>;
  status = "disabled";
 };

 rkcif_mipi_lvds2_sditf_vir2: rkcif-mipi-lvds2-sditf-vir2 {
  compatible = "rockchip,rkcif-sditf";
  rockchip,cif = <&rkcif_mipi_lvds2>;
  status = "disabled";
 };

 rkcif_mipi_lvds2_sditf_vir3: rkcif-mipi-lvds2-sditf-vir3 {
  compatible = "rockchip,rkcif-sditf";
  rockchip,cif = <&rkcif_mipi_lvds2>;
  status = "disabled";
 };

-------------------------------------------

rkcif_mipi_lvds3: rkcif-mipi-lvds3 {
  compatible = "rockchip,rkcif-mipi-lvds";
  rockchip,hw = <&rkcif>;
  iommus = <&rkcif_mmu>;
  status = "disabled";
 };

 rkcif_mipi_lvds3_sditf: rkcif-mipi-lvds3-sditf {
  compatible = "rockchip,rkcif-sditf";
  rockchip,cif = <&rkcif_mipi_lvds3>;
  status = "disabled";
 };

 rkcif_mipi_lvds3_sditf_vir1: rkcif-mipi-lvds3-sditf-vir1 {
  compatible = "rockchip,rkcif-sditf";
  rockchip,cif = <&rkcif_mipi_lvds3>;
  status = "disabled";
 };

 rkcif_mipi_lvds3_sditf_vir2: rkcif-mipi-lvds3-sditf-vir2 {
  compatible = "rockchip,rkcif-sditf";
  rockchip,cif = <&rkcif_mipi_lvds3>;
  status = "disabled";
 };

 rkcif_mipi_lvds3_sditf_vir3: rkcif-mipi-lvds3-sditf-vir3 {
  compatible = "rockchip,rkcif-sditf";
  rockchip,cif = <&rkcif_mipi_lvds3>;
  status = "disabled";
 };

-------------------------------------------

rkisp0_vir0: rkisp0-vir0 {
  compatible = "rockchip,rkisp-vir";
  rockchip,hw = <&rkisp0>;





  status = "disabled";
 };

 rkisp0_vir1: rkisp0-vir1 {
  compatible = "rockchip,rkisp-vir";
  rockchip,hw = <&rkisp0>;
  status = "disabled";
 };

 rkisp0_vir2: rkisp0-vir2 {
  compatible = "rockchip,rkisp-vir";
  rockchip,hw = <&rkisp0>;
  status = "disabled";
 };

 rkisp0_vir3: rkisp0-vir3 {
  compatible = "rockchip,rkisp-vir";
  rockchip,hw = <&rkisp0>;
  status = "disabled";
 };
 
 -------------------------------------------

rkisp1_vir0: rkisp1-vir0 {
  compatible = "rockchip,rkisp-vir";
  rockchip,hw = <&rkisp1>;
  status = "disabled";
 };

 rkisp1_vir1: rkisp1-vir1 {
  compatible = "rockchip,rkisp-vir";
  rockchip,hw = <&rkisp1>;
  status = "disabled";
 };

 rkisp1_vir2: rkisp1-vir2 {
  compatible = "rockchip,rkisp-vir";
  rockchip,hw = <&rkisp1>;
  status = "disabled";
 };

 rkisp1_vir3: rkisp1-vir3 {
   compatible = "rockchip,rkisp-vir";
  rockchip,hw = <&rkisp1>;
  status = "disabled";
 };

 -------------------------------------------
 
 rkisp0: rkisp@fdcb0000 {
  compatible = "rockchip,rk3588-rkisp";
  reg = <0x0 0xfdcb0000 0x0 0x7f00>;
  interrupts = <0 131 4>,
        <0 133 4>,
        <0 134 4>;
  interrupt-names = "isp_irq", "mi_irq", "mipi_irq";
  clocks = <&cru 478>, <&cru 479>,
    <&cru 475>, <&cru 476>,
    <&cru 477>;
  clock-names = "aclk_isp", "hclk_isp", "clk_isp_core",
         "clk_isp_core_marvin", "clk_isp_core_vicap";
  power-domains = <&power 27>;
  iommus = <&isp0_mmu>;
  status = "disabled";
 };



 isp0_mmu: iommu@fdcb7f00 {
  compatible = "rockchip,iommu-v2";
  reg = <0x0 0xfdcb7f00 0x0 0x100>;
  interrupts = <0 132 4>;
  interrupt-names = "isp0_mmu";
  clocks = <&cru 478>, <&cru 479>;
  clock-names = "aclk", "iface";
  power-domains = <&power 27>;
  #iommu-cells = <0>;
  rockchip,disable-mmu-reset;
  status = "disabled";
 };

 rkisp1: rkisp@fdcc0000 {
  compatible = "rockchip,rk3588-rkisp";
  reg = <0x0 0xfdcc0000 0x0 0x7f00>;
  interrupts = <0 135 4>,
        <0 137 4>,
              <0 138 4>;
  interrupt-names = "isp_irq", "mi_irq", "mipi_irq";
  clocks = <&cru 288>, <&cru 289>,
    <&cru 285>, <&cru 286>,
    <&cru 287>;
  clock-names = "aclk_isp", "hclk_isp", "clk_isp_core",
         "clk_isp_core_marvin", "clk_isp_core_vicap";
  power-domains = <&power 28>;
  iommus = <&isp1_mmu>;
  status = "disabled";
 };

 isp1_mmu: iommu@fdcc7f00 {
  compatible = "rockchip,iommu-v2";
  reg = <0x0 0xfdcc7f00 0x0 0x100>;
  interrupts = <0 136 4>;
  interrupt-names = "isp1_mmu";
  clocks = <&cru 288>, <&cru 289>;
  clock-names = "aclk", "iface";
  power-domains = <&power 28>;
  #iommu-cells = <0>;
  rockchip,disable-mmu-reset;
  status = "disabled";
 };
 
   -------------------------------------------
   
  rkisp_unite: rkisp-unite@fdcb0000 {
  compatible = "rockchip,rk3588-rkisp-unite";
  reg = <0x0 0xfdcb0000 0x0 0x10000>,
        <0x0 0xfdcc0000 0x0 0x10000>;
  interrupts = <0 135 4>,
        <0 137 4>,
        <0 138 4>;
  interrupt-names = "isp_irq", "mi_irq", "mipi_irq";
  clocks = <&cru 478>, <&cru 479>,
    <&cru 475>, <&cru 476>,
    <&cru 477>, <&cru 288>,
    <&cru 289>, <&cru 285>,
    <&cru 286>, <&cru 287>;
  clock-names = "aclk_isp0", "hclk_isp0", "clk_isp_core0",
         "clk_isp_core_marvin0", "clk_isp_core_vicap0",
         "aclk_isp1", "hclk_isp1", "clk_isp_core1",
         "clk_isp_core_marvin1", "clk_isp_core_vicap1";
  power-domains = <&power 28>;
  iommus = <&rkisp_unite_mmu>;
  status = "disabled";
 };

  rkisp_unite_mmu: rkisp-unite-mmu@fdcb7f00 {
  compatible = "rockchip,iommu-v2";
  reg = <0x0 0xfdcb7f00 0x0 0x100>, <0x0 0xfdcc7f00 0x0 0x100>;
  interrupts = <0 132 4>,
              <0 136 4>;
  interrupt-names = "isp0_mmu", "isp1_mmu";
  clocks = <&cru 478>, <&cru 479>,
    <&cru 288>, <&cru 289>;
  clock-names = "aclk0", "iface0", "aclk1", "iface1";
  power-domains = <&power 28>;
  #iommu-cells = <0>;
  rockchip,disable-mmu-reset;
  status = "disabled";
 };
 
 
 
  -------------------------------------------
  
 rkispp0: rkispp@fdcd0000 {
  compatible = "rockchip,rk3588-rkispp";
  reg = <0x0 0xfdcd0000 0x0 0x0f00>;
  interrupts = <0 139 4>;
  interrupt-names = "fec_irq";
  clocks = <&cru 469>, <&cru 470>,
    <&cru 471>;
  clock-names = "aclk_ispp", "hclk_ispp", "clk_ispp";
  assigned-clocks = <&cru 470>;
  assigned-clock-rates = <100000000>;
  power-domains = <&power 29>;
  iommus = <&fec0_mmu>;
  status = "disabled";
 };


rkispp0_vir0: rkispp0-vir0 {
  compatible = "rockchip,rk3588-rkispp-vir";
  rockchip,hw = <&rkispp0>;
  status = "disabled";
 };
 
 rkispp1: rkispp@fdcd8000 {
  compatible = "rockchip,rk3588-rkispp";
  reg = <0x0 0xfdcd8000 0x0 0x0f00>;
  interrupts = <0 141 4>;
  interrupt-names = "fec_irq";
  clocks = <&cru 472>, <&cru 473>,
    <&cru 474>;
  clock-names = "aclk_ispp", "hclk_ispp", "clk_ispp";
  assigned-clocks = <&cru 473>;
  assigned-clock-rates = <100000000>;
  power-domains = <&power 29>;
  iommus = <&fec1_mmu>;
  status = "disabled";
 };       

 rkispp1_vir0: rkispp1-vir0 {
  compatible = "rockchip,rk3588-rkispp-vir";
  rockchip,hw = <&rkispp1>;
  status = "disabled";
 };