任意整数分频器 verilog代码实现，testbench仿真

直接上代码吧，将奇数以及偶数分频合并在一起，需要注意当分频数为1时情况的书写

module test01(
		input clk_in,
		input rst_n,
		output clk_out);
                

		localparam div_width = 3, //分频计数器位宽
		            fre_div = 7; //分频数
		
		reg clk_even;
		reg [div_width-1:0] clk_even_cnt;  //偶数计数器
		reg clk_1,clk_2;
		wire clk_odd;
		reg [div_width-1:0] clk_1_cnt,clk_2_cnt; //奇数计数器

                     assign clk_out = (fre_div == 1'b1)? clk_in : (fre_div[0]? clk_odd : clk_even); //输出
                     assign clk_odd = clk_1 | clk_2;

//偶数分频情况
	 	always @ (posedge clk_in or negedge rst_n)
			begin
			       if (!rst_n)
			            begin
				            clk_even <= 1'b0;
    				        clk_even_cnt <= 0;
			            end
		           else if (clk_even_cnt == fre_div/2-1)
                        begin
				            clk_even <= ~clk_even;
    				        clk_even_cnt <= clk_even_cnt + 1'b1;
			            end
                   else if (clk_even_cnt == fre_div - 1)
                        begin
				            clk_even <= ~clk_even;
    			            clk_even_cnt <= 0;
			            end
		           else
                        begin
			             	clk_even <= clk_even;
    				        clk_even_cnt <= clk_even_cnt + 1'b1;
			            end
			end


//奇数分频情况
       always @ (posedge clk_in or negedge rst_n)
			begin
			      if (!rst_n)
			            begin
				           clk_1 <= 1'b0;
    				       clk_1_cnt <= 0;
			            end
		          else if (clk_1_cnt  == (fre_div-1)/2)
                        begin
				           clk_1 <= ~clk_1;
    				       clk_1_cnt  <= clk_1_cnt + 1'b1;
			            end
                 else if (clk_1_cnt  == fre_div - 1)
                        begin
				           clk_1 <= ~clk_1;
    				       clk_1_cnt  <= 0;
			            end
		        else
                        begin
				           clk_1 <= clk_1;
    				       clk_1_cnt  <= clk_1_cnt  + 1'b1;
			            end
			end

      always @ (negedge clk_in or negedge rst_n)
			begin
			       if (!rst_n)
			           begin
				         clk_2 <= 1'b0;
    				     clk_2_cnt <= 0;
			           end
		          else if (clk_2_cnt  == (fre_div-1)/2)
                       begin
				         clk_2 <= ~clk_2;
    				     clk_2_cnt  <= clk_2_cnt  + 1'b1;
			           end
                 else if (clk_2_cnt  == fre_div - 1)
                        begin
  				           clk_2 <= ~clk_1;
  				           clk_2_cnt  <= 0;
			           end
		        else
                       begin
				         clk_2 <= clk_1;
    				     clk_2_cnt  <= clk_2_cnt  + 1'b1;
			            end
			end

endmodule

测试文件

`timescale 1ns / 1ps

module sim_test_01;
             reg clk_in;
             reg rst_n;
             wire clk_out;
             
      test01 mo(
		.clk_in(clk_in),
		.rst_n(rst_n),
		.clk_out(clk_out)); 
             
             initial 
                    begin
                          clk_in = 1'b0;
                          rst_n = 1'b1;
                          #20 rst_n = 1'b0;
                          #20 rst_n = 1'b1;
                    end
              
             always #10 clk_in = ~clk_in;
             
endmodule

分频数div_fre为1时

分频数div_fre为偶数时

分频数div_fre为奇数时

欢迎批评指正！